1 /* 2 * Copyright 2011-2014 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/genalloc.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_platform.h> 23 #include <linux/regmap.h> 24 #include <linux/suspend.h> 25 #include <asm/cacheflush.h> 26 #include <asm/fncpy.h> 27 #include <asm/proc-fns.h> 28 #include <asm/suspend.h> 29 #include <asm/tlb.h> 30 31 #include "common.h" 32 #include "hardware.h" 33 34 #define CCR 0x0 35 #define BM_CCR_WB_COUNT (0x7 << 16) 36 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 37 #define BM_CCR_RBC_EN (0x1 << 27) 38 39 #define CLPCR 0x54 40 #define BP_CLPCR_LPM 0 41 #define BM_CLPCR_LPM (0x3 << 0) 42 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 44 #define BM_CLPCR_SBYOS (0x1 << 6) 45 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) 46 #define BM_CLPCR_VSTBY (0x1 << 8) 47 #define BP_CLPCR_STBY_COUNT 9 48 #define BM_CLPCR_STBY_COUNT (0x3 << 9) 49 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) 50 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) 51 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) 52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) 53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) 54 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) 55 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) 56 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) 57 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) 58 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 59 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 60 61 #define CGPR 0x64 62 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) 63 64 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 65 #define MX6_MAX_MMDC_IO_NUM 33 66 67 static void __iomem *ccm_base; 68 static void __iomem *suspend_ocram_base; 69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); 70 71 /* 72 * suspend ocram space layout: 73 * ======================== high address ====================== 74 * . 75 * . 76 * . 77 * ^ 78 * ^ 79 * ^ 80 * imx6_suspend code 81 * PM_INFO structure(imx6_cpu_pm_info) 82 * ======================== low address ======================= 83 */ 84 85 struct imx6_pm_base { 86 phys_addr_t pbase; 87 void __iomem *vbase; 88 }; 89 90 struct imx6_pm_socdata { 91 u32 ddr_type; 92 const char *mmdc_compat; 93 const char *src_compat; 94 const char *iomuxc_compat; 95 const char *gpc_compat; 96 const u32 mmdc_io_num; 97 const u32 *mmdc_io_offset; 98 }; 99 100 static const u32 imx6q_mmdc_io_offset[] __initconst = { 101 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ 102 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ 103 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 104 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ 105 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ 106 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ 107 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 108 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ 109 0x74c, /* GPR_ADDS */ 110 }; 111 112 static const u32 imx6dl_mmdc_io_offset[] __initconst = { 113 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 114 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ 115 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 116 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ 117 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ 118 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ 119 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 120 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ 121 0x74c, /* GPR_ADDS */ 122 }; 123 124 static const u32 imx6sl_mmdc_io_offset[] __initconst = { 125 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ 126 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ 127 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 128 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ 129 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ 130 }; 131 132 static const u32 imx6sx_mmdc_io_offset[] __initconst = { 133 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 134 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ 135 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 136 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ 137 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ 138 }; 139 140 static const struct imx6_pm_socdata imx6q_pm_data __initconst = { 141 .mmdc_compat = "fsl,imx6q-mmdc", 142 .src_compat = "fsl,imx6q-src", 143 .iomuxc_compat = "fsl,imx6q-iomuxc", 144 .gpc_compat = "fsl,imx6q-gpc", 145 .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), 146 .mmdc_io_offset = imx6q_mmdc_io_offset, 147 }; 148 149 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 150 .mmdc_compat = "fsl,imx6q-mmdc", 151 .src_compat = "fsl,imx6q-src", 152 .iomuxc_compat = "fsl,imx6dl-iomuxc", 153 .gpc_compat = "fsl,imx6q-gpc", 154 .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), 155 .mmdc_io_offset = imx6dl_mmdc_io_offset, 156 }; 157 158 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 159 .mmdc_compat = "fsl,imx6sl-mmdc", 160 .src_compat = "fsl,imx6sl-src", 161 .iomuxc_compat = "fsl,imx6sl-iomuxc", 162 .gpc_compat = "fsl,imx6sl-gpc", 163 .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), 164 .mmdc_io_offset = imx6sl_mmdc_io_offset, 165 }; 166 167 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { 168 .mmdc_compat = "fsl,imx6sx-mmdc", 169 .src_compat = "fsl,imx6sx-src", 170 .iomuxc_compat = "fsl,imx6sx-iomuxc", 171 .gpc_compat = "fsl,imx6sx-gpc", 172 .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), 173 .mmdc_io_offset = imx6sx_mmdc_io_offset, 174 }; 175 176 /* 177 * This structure is for passing necessary data for low level ocram 178 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct 179 * definition is changed, the offset definition in 180 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, 181 * otherwise, the suspend to ocram function will be broken! 182 */ 183 struct imx6_cpu_pm_info { 184 phys_addr_t pbase; /* The physical address of pm_info. */ 185 phys_addr_t resume_addr; /* The physical resume address for asm code */ 186 u32 ddr_type; 187 u32 pm_info_size; /* Size of pm_info. */ 188 struct imx6_pm_base mmdc_base; 189 struct imx6_pm_base src_base; 190 struct imx6_pm_base iomuxc_base; 191 struct imx6_pm_base ccm_base; 192 struct imx6_pm_base gpc_base; 193 struct imx6_pm_base l2_base; 194 u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ 195 u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ 196 } __aligned(8); 197 198 void imx6q_set_int_mem_clk_lpm(bool enable) 199 { 200 u32 val = readl_relaxed(ccm_base + CGPR); 201 202 val &= ~BM_CGPR_INT_MEM_CLK_LPM; 203 if (enable) 204 val |= BM_CGPR_INT_MEM_CLK_LPM; 205 writel_relaxed(val, ccm_base + CGPR); 206 } 207 208 static void imx6q_enable_rbc(bool enable) 209 { 210 u32 val; 211 212 /* 213 * need to mask all interrupts in GPC before 214 * operating RBC configurations 215 */ 216 imx_gpc_mask_all(); 217 218 /* configure RBC enable bit */ 219 val = readl_relaxed(ccm_base + CCR); 220 val &= ~BM_CCR_RBC_EN; 221 val |= enable ? BM_CCR_RBC_EN : 0; 222 writel_relaxed(val, ccm_base + CCR); 223 224 /* configure RBC count */ 225 val = readl_relaxed(ccm_base + CCR); 226 val &= ~BM_CCR_RBC_BYPASS_COUNT; 227 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; 228 writel(val, ccm_base + CCR); 229 230 /* 231 * need to delay at least 2 cycles of CKIL(32K) 232 * due to hardware design requirement, which is 233 * ~61us, here we use 65us for safe 234 */ 235 udelay(65); 236 237 /* restore GPC interrupt mask settings */ 238 imx_gpc_restore_all(); 239 } 240 241 static void imx6q_enable_wb(bool enable) 242 { 243 u32 val; 244 245 /* configure well bias enable bit */ 246 val = readl_relaxed(ccm_base + CLPCR); 247 val &= ~BM_CLPCR_WB_PER_AT_LPM; 248 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; 249 writel_relaxed(val, ccm_base + CLPCR); 250 251 /* configure well bias count */ 252 val = readl_relaxed(ccm_base + CCR); 253 val &= ~BM_CCR_WB_COUNT; 254 val |= enable ? BM_CCR_WB_COUNT : 0; 255 writel_relaxed(val, ccm_base + CCR); 256 } 257 258 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 259 { 260 u32 val = readl_relaxed(ccm_base + CLPCR); 261 262 val &= ~BM_CLPCR_LPM; 263 switch (mode) { 264 case WAIT_CLOCKED: 265 break; 266 case WAIT_UNCLOCKED: 267 val |= 0x1 << BP_CLPCR_LPM; 268 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; 269 break; 270 case STOP_POWER_ON: 271 val |= 0x2 << BP_CLPCR_LPM; 272 val &= ~BM_CLPCR_VSTBY; 273 val &= ~BM_CLPCR_SBYOS; 274 if (cpu_is_imx6sl()) 275 val |= BM_CLPCR_BYPASS_PMIC_READY; 276 if (cpu_is_imx6sl() || cpu_is_imx6sx()) 277 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 278 else 279 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 280 break; 281 case WAIT_UNCLOCKED_POWER_OFF: 282 val |= 0x1 << BP_CLPCR_LPM; 283 val &= ~BM_CLPCR_VSTBY; 284 val &= ~BM_CLPCR_SBYOS; 285 break; 286 case STOP_POWER_OFF: 287 val |= 0x2 << BP_CLPCR_LPM; 288 val |= 0x3 << BP_CLPCR_STBY_COUNT; 289 val |= BM_CLPCR_VSTBY; 290 val |= BM_CLPCR_SBYOS; 291 if (cpu_is_imx6sl()) 292 val |= BM_CLPCR_BYPASS_PMIC_READY; 293 if (cpu_is_imx6sl() || cpu_is_imx6sx()) 294 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 295 else 296 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 297 break; 298 default: 299 return -EINVAL; 300 } 301 302 /* 303 * ERR007265: CCM: When improper low-power sequence is used, 304 * the SoC enters low power mode before the ARM core executes WFI. 305 * 306 * Software workaround: 307 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending 308 * by setting IOMUX_GPR1_GINT. 309 * 2) Software should then unmask IRQ #32 in GPC before setting CCM 310 * Low-Power mode. 311 * 3) Software should mask IRQ #32 right after CCM Low-Power mode 312 * is set (set bits 0-1 of CCM_CLPCR). 313 */ 314 imx_gpc_hwirq_unmask(32); 315 writel_relaxed(val, ccm_base + CLPCR); 316 imx_gpc_hwirq_mask(32); 317 318 return 0; 319 } 320 321 static int imx6q_suspend_finish(unsigned long val) 322 { 323 if (!imx6_suspend_in_ocram_fn) { 324 cpu_do_idle(); 325 } else { 326 /* 327 * call low level suspend function in ocram, 328 * as we need to float DDR IO. 329 */ 330 local_flush_tlb_all(); 331 imx6_suspend_in_ocram_fn(suspend_ocram_base); 332 } 333 334 return 0; 335 } 336 337 static int imx6q_pm_enter(suspend_state_t state) 338 { 339 switch (state) { 340 case PM_SUSPEND_STANDBY: 341 imx6q_set_lpm(STOP_POWER_ON); 342 imx6q_set_int_mem_clk_lpm(true); 343 imx_gpc_pre_suspend(false); 344 if (cpu_is_imx6sl()) 345 imx6sl_set_wait_clk(true); 346 /* Zzz ... */ 347 cpu_do_idle(); 348 if (cpu_is_imx6sl()) 349 imx6sl_set_wait_clk(false); 350 imx_gpc_post_resume(); 351 imx6q_set_lpm(WAIT_CLOCKED); 352 break; 353 case PM_SUSPEND_MEM: 354 imx6q_set_lpm(STOP_POWER_OFF); 355 imx6q_set_int_mem_clk_lpm(false); 356 imx6q_enable_wb(true); 357 /* 358 * For suspend into ocram, asm code already take care of 359 * RBC setting, so we do NOT need to do that here. 360 */ 361 if (!imx6_suspend_in_ocram_fn) 362 imx6q_enable_rbc(true); 363 imx_gpc_pre_suspend(true); 364 imx_anatop_pre_suspend(); 365 imx_set_cpu_jump(0, v7_cpu_resume); 366 /* Zzz ... */ 367 cpu_suspend(0, imx6q_suspend_finish); 368 if (cpu_is_imx6q() || cpu_is_imx6dl()) 369 imx_smp_prepare(); 370 imx_anatop_post_resume(); 371 imx_gpc_post_resume(); 372 imx6q_enable_rbc(false); 373 imx6q_enable_wb(false); 374 imx6q_set_int_mem_clk_lpm(true); 375 imx6q_set_lpm(WAIT_CLOCKED); 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int imx6q_pm_valid(suspend_state_t state) 385 { 386 return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); 387 } 388 389 static const struct platform_suspend_ops imx6q_pm_ops = { 390 .enter = imx6q_pm_enter, 391 .valid = imx6q_pm_valid, 392 }; 393 394 void __init imx6q_pm_set_ccm_base(void __iomem *base) 395 { 396 ccm_base = base; 397 } 398 399 static int __init imx6_pm_get_base(struct imx6_pm_base *base, 400 const char *compat) 401 { 402 struct device_node *node; 403 struct resource res; 404 int ret = 0; 405 406 node = of_find_compatible_node(NULL, NULL, compat); 407 if (!node) { 408 ret = -ENODEV; 409 goto out; 410 } 411 412 ret = of_address_to_resource(node, 0, &res); 413 if (ret) 414 goto put_node; 415 416 base->pbase = res.start; 417 base->vbase = ioremap(res.start, resource_size(&res)); 418 if (!base->vbase) 419 ret = -ENOMEM; 420 421 put_node: 422 of_node_put(node); 423 out: 424 return ret; 425 } 426 427 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) 428 { 429 phys_addr_t ocram_pbase; 430 struct device_node *node; 431 struct platform_device *pdev; 432 struct imx6_cpu_pm_info *pm_info; 433 struct gen_pool *ocram_pool; 434 unsigned long ocram_base; 435 int i, ret = 0; 436 const u32 *mmdc_offset_array; 437 438 suspend_set_ops(&imx6q_pm_ops); 439 440 if (!socdata) { 441 pr_warn("%s: invalid argument!\n", __func__); 442 return -EINVAL; 443 } 444 445 node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 446 if (!node) { 447 pr_warn("%s: failed to find ocram node!\n", __func__); 448 return -ENODEV; 449 } 450 451 pdev = of_find_device_by_node(node); 452 if (!pdev) { 453 pr_warn("%s: failed to find ocram device!\n", __func__); 454 ret = -ENODEV; 455 goto put_node; 456 } 457 458 ocram_pool = dev_get_gen_pool(&pdev->dev); 459 if (!ocram_pool) { 460 pr_warn("%s: ocram pool unavailable!\n", __func__); 461 ret = -ENODEV; 462 goto put_node; 463 } 464 465 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); 466 if (!ocram_base) { 467 pr_warn("%s: unable to alloc ocram!\n", __func__); 468 ret = -ENOMEM; 469 goto put_node; 470 } 471 472 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); 473 474 suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, 475 MX6Q_SUSPEND_OCRAM_SIZE, false); 476 477 pm_info = suspend_ocram_base; 478 pm_info->pbase = ocram_pbase; 479 pm_info->resume_addr = virt_to_phys(v7_cpu_resume); 480 pm_info->pm_info_size = sizeof(*pm_info); 481 482 /* 483 * ccm physical address is not used by asm code currently, 484 * so get ccm virtual address directly, as we already have 485 * it from ccm driver. 486 */ 487 pm_info->ccm_base.vbase = ccm_base; 488 489 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); 490 if (ret) { 491 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); 492 goto put_node; 493 } 494 495 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); 496 if (ret) { 497 pr_warn("%s: failed to get src base %d!\n", __func__, ret); 498 goto src_map_failed; 499 } 500 501 ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); 502 if (ret) { 503 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); 504 goto iomuxc_map_failed; 505 } 506 507 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); 508 if (ret) { 509 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); 510 goto gpc_map_failed; 511 } 512 513 ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache"); 514 if (ret) { 515 pr_warn("%s: failed to get pl310-cache base %d!\n", 516 __func__, ret); 517 goto pl310_cache_map_failed; 518 } 519 520 pm_info->ddr_type = imx_mmdc_get_ddr_type(); 521 pm_info->mmdc_io_num = socdata->mmdc_io_num; 522 mmdc_offset_array = socdata->mmdc_io_offset; 523 524 for (i = 0; i < pm_info->mmdc_io_num; i++) { 525 pm_info->mmdc_io_val[i][0] = 526 mmdc_offset_array[i]; 527 pm_info->mmdc_io_val[i][1] = 528 readl_relaxed(pm_info->iomuxc_base.vbase + 529 mmdc_offset_array[i]); 530 } 531 532 imx6_suspend_in_ocram_fn = fncpy( 533 suspend_ocram_base + sizeof(*pm_info), 534 &imx6_suspend, 535 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); 536 537 goto put_node; 538 539 pl310_cache_map_failed: 540 iounmap(&pm_info->gpc_base.vbase); 541 gpc_map_failed: 542 iounmap(&pm_info->iomuxc_base.vbase); 543 iomuxc_map_failed: 544 iounmap(&pm_info->src_base.vbase); 545 src_map_failed: 546 iounmap(&pm_info->mmdc_base.vbase); 547 put_node: 548 of_node_put(node); 549 550 return ret; 551 } 552 553 static void __init imx6_pm_common_init(const struct imx6_pm_socdata 554 *socdata) 555 { 556 struct regmap *gpr; 557 int ret; 558 559 WARN_ON(!ccm_base); 560 561 if (IS_ENABLED(CONFIG_SUSPEND)) { 562 ret = imx6q_suspend_init(socdata); 563 if (ret) 564 pr_warn("%s: No DDR LPM support with suspend %d!\n", 565 __func__, ret); 566 } 567 568 /* 569 * This is for SW workaround step #1 of ERR007265, see comments 570 * in imx6q_set_lpm for details of this errata. 571 * Force IOMUXC irq pending, so that the interrupt to GPC can be 572 * used to deassert dsm_request signal when the signal gets 573 * asserted unexpectedly. 574 */ 575 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 576 if (!IS_ERR(gpr)) 577 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, 578 IMX6Q_GPR1_GINT); 579 } 580 581 void __init imx6q_pm_init(void) 582 { 583 imx6_pm_common_init(&imx6q_pm_data); 584 } 585 586 void __init imx6dl_pm_init(void) 587 { 588 imx6_pm_common_init(&imx6dl_pm_data); 589 } 590 591 void __init imx6sl_pm_init(void) 592 { 593 imx6_pm_common_init(&imx6sl_pm_data); 594 } 595 596 void __init imx6sx_pm_init(void) 597 { 598 imx6_pm_common_init(&imx6sx_pm_data); 599 } 600