1 /* 2 * Copyright 2011-2014 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/genalloc.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_platform.h> 23 #include <linux/regmap.h> 24 #include <linux/suspend.h> 25 #include <asm/cacheflush.h> 26 #include <asm/fncpy.h> 27 #include <asm/proc-fns.h> 28 #include <asm/suspend.h> 29 #include <asm/tlb.h> 30 31 #include "common.h" 32 #include "hardware.h" 33 34 #define CCR 0x0 35 #define BM_CCR_WB_COUNT (0x7 << 16) 36 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 37 #define BM_CCR_RBC_EN (0x1 << 27) 38 39 #define CLPCR 0x54 40 #define BP_CLPCR_LPM 0 41 #define BM_CLPCR_LPM (0x3 << 0) 42 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 44 #define BM_CLPCR_SBYOS (0x1 << 6) 45 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) 46 #define BM_CLPCR_VSTBY (0x1 << 8) 47 #define BP_CLPCR_STBY_COUNT 9 48 #define BM_CLPCR_STBY_COUNT (0x3 << 9) 49 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) 50 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) 51 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) 52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) 53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) 54 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) 55 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) 56 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) 57 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) 58 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 59 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 60 61 #define CGPR 0x64 62 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) 63 64 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 65 #define MX6_MAX_MMDC_IO_NUM 33 66 67 static void __iomem *ccm_base; 68 static void __iomem *suspend_ocram_base; 69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); 70 71 /* 72 * suspend ocram space layout: 73 * ======================== high address ====================== 74 * . 75 * . 76 * . 77 * ^ 78 * ^ 79 * ^ 80 * imx6_suspend code 81 * PM_INFO structure(imx6_cpu_pm_info) 82 * ======================== low address ======================= 83 */ 84 85 struct imx6_pm_base { 86 phys_addr_t pbase; 87 void __iomem *vbase; 88 }; 89 90 struct imx6_pm_socdata { 91 u32 cpu_type; 92 const char *mmdc_compat; 93 const char *src_compat; 94 const char *iomuxc_compat; 95 const char *gpc_compat; 96 const u32 mmdc_io_num; 97 const u32 *mmdc_io_offset; 98 }; 99 100 static const u32 imx6q_mmdc_io_offset[] __initconst = { 101 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ 102 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ 103 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 104 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ 105 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ 106 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ 107 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 108 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ 109 0x74c, /* GPR_ADDS */ 110 }; 111 112 static const u32 imx6dl_mmdc_io_offset[] __initconst = { 113 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 114 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ 115 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 116 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ 117 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ 118 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ 119 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 120 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ 121 0x74c, /* GPR_ADDS */ 122 }; 123 124 static const u32 imx6sl_mmdc_io_offset[] __initconst = { 125 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ 126 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ 127 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 128 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ 129 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ 130 }; 131 132 static const struct imx6_pm_socdata imx6q_pm_data __initconst = { 133 .cpu_type = MXC_CPU_IMX6Q, 134 .mmdc_compat = "fsl,imx6q-mmdc", 135 .src_compat = "fsl,imx6q-src", 136 .iomuxc_compat = "fsl,imx6q-iomuxc", 137 .gpc_compat = "fsl,imx6q-gpc", 138 .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), 139 .mmdc_io_offset = imx6q_mmdc_io_offset, 140 }; 141 142 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 143 .cpu_type = MXC_CPU_IMX6DL, 144 .mmdc_compat = "fsl,imx6q-mmdc", 145 .src_compat = "fsl,imx6q-src", 146 .iomuxc_compat = "fsl,imx6dl-iomuxc", 147 .gpc_compat = "fsl,imx6q-gpc", 148 .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), 149 .mmdc_io_offset = imx6dl_mmdc_io_offset, 150 }; 151 152 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 153 .cpu_type = MXC_CPU_IMX6SL, 154 .mmdc_compat = "fsl,imx6sl-mmdc", 155 .src_compat = "fsl,imx6sl-src", 156 .iomuxc_compat = "fsl,imx6sl-iomuxc", 157 .gpc_compat = "fsl,imx6sl-gpc", 158 .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), 159 .mmdc_io_offset = imx6sl_mmdc_io_offset, 160 }; 161 162 /* 163 * This structure is for passing necessary data for low level ocram 164 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct 165 * definition is changed, the offset definition in 166 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, 167 * otherwise, the suspend to ocram function will be broken! 168 */ 169 struct imx6_cpu_pm_info { 170 phys_addr_t pbase; /* The physical address of pm_info. */ 171 phys_addr_t resume_addr; /* The physical resume address for asm code */ 172 u32 cpu_type; 173 u32 pm_info_size; /* Size of pm_info. */ 174 struct imx6_pm_base mmdc_base; 175 struct imx6_pm_base src_base; 176 struct imx6_pm_base iomuxc_base; 177 struct imx6_pm_base ccm_base; 178 struct imx6_pm_base gpc_base; 179 struct imx6_pm_base l2_base; 180 u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ 181 u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ 182 } __aligned(8); 183 184 void imx6q_set_int_mem_clk_lpm(void) 185 { 186 u32 val = readl_relaxed(ccm_base + CGPR); 187 188 val |= BM_CGPR_INT_MEM_CLK_LPM; 189 writel_relaxed(val, ccm_base + CGPR); 190 } 191 192 static void imx6q_enable_rbc(bool enable) 193 { 194 u32 val; 195 196 /* 197 * need to mask all interrupts in GPC before 198 * operating RBC configurations 199 */ 200 imx_gpc_mask_all(); 201 202 /* configure RBC enable bit */ 203 val = readl_relaxed(ccm_base + CCR); 204 val &= ~BM_CCR_RBC_EN; 205 val |= enable ? BM_CCR_RBC_EN : 0; 206 writel_relaxed(val, ccm_base + CCR); 207 208 /* configure RBC count */ 209 val = readl_relaxed(ccm_base + CCR); 210 val &= ~BM_CCR_RBC_BYPASS_COUNT; 211 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; 212 writel(val, ccm_base + CCR); 213 214 /* 215 * need to delay at least 2 cycles of CKIL(32K) 216 * due to hardware design requirement, which is 217 * ~61us, here we use 65us for safe 218 */ 219 udelay(65); 220 221 /* restore GPC interrupt mask settings */ 222 imx_gpc_restore_all(); 223 } 224 225 static void imx6q_enable_wb(bool enable) 226 { 227 u32 val; 228 229 /* configure well bias enable bit */ 230 val = readl_relaxed(ccm_base + CLPCR); 231 val &= ~BM_CLPCR_WB_PER_AT_LPM; 232 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; 233 writel_relaxed(val, ccm_base + CLPCR); 234 235 /* configure well bias count */ 236 val = readl_relaxed(ccm_base + CCR); 237 val &= ~BM_CCR_WB_COUNT; 238 val |= enable ? BM_CCR_WB_COUNT : 0; 239 writel_relaxed(val, ccm_base + CCR); 240 } 241 242 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 243 { 244 struct irq_data *iomuxc_irq_data = irq_get_irq_data(32); 245 u32 val = readl_relaxed(ccm_base + CLPCR); 246 247 val &= ~BM_CLPCR_LPM; 248 switch (mode) { 249 case WAIT_CLOCKED: 250 break; 251 case WAIT_UNCLOCKED: 252 val |= 0x1 << BP_CLPCR_LPM; 253 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; 254 break; 255 case STOP_POWER_ON: 256 val |= 0x2 << BP_CLPCR_LPM; 257 break; 258 case WAIT_UNCLOCKED_POWER_OFF: 259 val |= 0x1 << BP_CLPCR_LPM; 260 val &= ~BM_CLPCR_VSTBY; 261 val &= ~BM_CLPCR_SBYOS; 262 break; 263 case STOP_POWER_OFF: 264 val |= 0x2 << BP_CLPCR_LPM; 265 val |= 0x3 << BP_CLPCR_STBY_COUNT; 266 val |= BM_CLPCR_VSTBY; 267 val |= BM_CLPCR_SBYOS; 268 if (cpu_is_imx6sl()) { 269 val |= BM_CLPCR_BYPASS_PMIC_READY; 270 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 271 } else { 272 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 273 } 274 break; 275 default: 276 return -EINVAL; 277 } 278 279 /* 280 * ERR007265: CCM: When improper low-power sequence is used, 281 * the SoC enters low power mode before the ARM core executes WFI. 282 * 283 * Software workaround: 284 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending 285 * by setting IOMUX_GPR1_GINT. 286 * 2) Software should then unmask IRQ #32 in GPC before setting CCM 287 * Low-Power mode. 288 * 3) Software should mask IRQ #32 right after CCM Low-Power mode 289 * is set (set bits 0-1 of CCM_CLPCR). 290 */ 291 imx_gpc_irq_unmask(iomuxc_irq_data); 292 writel_relaxed(val, ccm_base + CLPCR); 293 imx_gpc_irq_mask(iomuxc_irq_data); 294 295 return 0; 296 } 297 298 static int imx6q_suspend_finish(unsigned long val) 299 { 300 if (!imx6_suspend_in_ocram_fn) { 301 cpu_do_idle(); 302 } else { 303 /* 304 * call low level suspend function in ocram, 305 * as we need to float DDR IO. 306 */ 307 local_flush_tlb_all(); 308 imx6_suspend_in_ocram_fn(suspend_ocram_base); 309 } 310 311 return 0; 312 } 313 314 static int imx6q_pm_enter(suspend_state_t state) 315 { 316 switch (state) { 317 case PM_SUSPEND_MEM: 318 imx6q_set_lpm(STOP_POWER_OFF); 319 imx6q_enable_wb(true); 320 /* 321 * For suspend into ocram, asm code already take care of 322 * RBC setting, so we do NOT need to do that here. 323 */ 324 if (!imx6_suspend_in_ocram_fn) 325 imx6q_enable_rbc(true); 326 imx_gpc_pre_suspend(); 327 imx_anatop_pre_suspend(); 328 imx_set_cpu_jump(0, v7_cpu_resume); 329 /* Zzz ... */ 330 cpu_suspend(0, imx6q_suspend_finish); 331 if (cpu_is_imx6q() || cpu_is_imx6dl()) 332 imx_smp_prepare(); 333 imx_anatop_post_resume(); 334 imx_gpc_post_resume(); 335 imx6q_enable_rbc(false); 336 imx6q_enable_wb(false); 337 imx6q_set_lpm(WAIT_CLOCKED); 338 break; 339 default: 340 return -EINVAL; 341 } 342 343 return 0; 344 } 345 346 static const struct platform_suspend_ops imx6q_pm_ops = { 347 .enter = imx6q_pm_enter, 348 .valid = suspend_valid_only_mem, 349 }; 350 351 void __init imx6q_pm_set_ccm_base(void __iomem *base) 352 { 353 ccm_base = base; 354 } 355 356 static int __init imx6_pm_get_base(struct imx6_pm_base *base, 357 const char *compat) 358 { 359 struct device_node *node; 360 struct resource res; 361 int ret = 0; 362 363 node = of_find_compatible_node(NULL, NULL, compat); 364 if (!node) { 365 ret = -ENODEV; 366 goto out; 367 } 368 369 ret = of_address_to_resource(node, 0, &res); 370 if (ret) 371 goto put_node; 372 373 base->pbase = res.start; 374 base->vbase = ioremap(res.start, resource_size(&res)); 375 if (!base->vbase) 376 ret = -ENOMEM; 377 378 put_node: 379 of_node_put(node); 380 out: 381 return ret; 382 } 383 384 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) 385 { 386 phys_addr_t ocram_pbase; 387 struct device_node *node; 388 struct platform_device *pdev; 389 struct imx6_cpu_pm_info *pm_info; 390 struct gen_pool *ocram_pool; 391 unsigned long ocram_base; 392 int i, ret = 0; 393 const u32 *mmdc_offset_array; 394 395 suspend_set_ops(&imx6q_pm_ops); 396 397 if (!socdata) { 398 pr_warn("%s: invalid argument!\n", __func__); 399 return -EINVAL; 400 } 401 402 node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 403 if (!node) { 404 pr_warn("%s: failed to find ocram node!\n", __func__); 405 return -ENODEV; 406 } 407 408 pdev = of_find_device_by_node(node); 409 if (!pdev) { 410 pr_warn("%s: failed to find ocram device!\n", __func__); 411 ret = -ENODEV; 412 goto put_node; 413 } 414 415 ocram_pool = dev_get_gen_pool(&pdev->dev); 416 if (!ocram_pool) { 417 pr_warn("%s: ocram pool unavailable!\n", __func__); 418 ret = -ENODEV; 419 goto put_node; 420 } 421 422 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); 423 if (!ocram_base) { 424 pr_warn("%s: unable to alloc ocram!\n", __func__); 425 ret = -ENOMEM; 426 goto put_node; 427 } 428 429 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); 430 431 suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, 432 MX6Q_SUSPEND_OCRAM_SIZE, false); 433 434 pm_info = suspend_ocram_base; 435 pm_info->pbase = ocram_pbase; 436 pm_info->resume_addr = virt_to_phys(v7_cpu_resume); 437 pm_info->pm_info_size = sizeof(*pm_info); 438 439 /* 440 * ccm physical address is not used by asm code currently, 441 * so get ccm virtual address directly, as we already have 442 * it from ccm driver. 443 */ 444 pm_info->ccm_base.vbase = ccm_base; 445 446 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); 447 if (ret) { 448 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); 449 goto put_node; 450 } 451 452 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); 453 if (ret) { 454 pr_warn("%s: failed to get src base %d!\n", __func__, ret); 455 goto src_map_failed; 456 } 457 458 ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); 459 if (ret) { 460 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); 461 goto iomuxc_map_failed; 462 } 463 464 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); 465 if (ret) { 466 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); 467 goto gpc_map_failed; 468 } 469 470 ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache"); 471 if (ret) { 472 pr_warn("%s: failed to get pl310-cache base %d!\n", 473 __func__, ret); 474 goto pl310_cache_map_failed; 475 } 476 477 pm_info->cpu_type = socdata->cpu_type; 478 pm_info->mmdc_io_num = socdata->mmdc_io_num; 479 mmdc_offset_array = socdata->mmdc_io_offset; 480 481 for (i = 0; i < pm_info->mmdc_io_num; i++) { 482 pm_info->mmdc_io_val[i][0] = 483 mmdc_offset_array[i]; 484 pm_info->mmdc_io_val[i][1] = 485 readl_relaxed(pm_info->iomuxc_base.vbase + 486 mmdc_offset_array[i]); 487 } 488 489 imx6_suspend_in_ocram_fn = fncpy( 490 suspend_ocram_base + sizeof(*pm_info), 491 &imx6_suspend, 492 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); 493 494 goto put_node; 495 496 pl310_cache_map_failed: 497 iounmap(&pm_info->gpc_base.vbase); 498 gpc_map_failed: 499 iounmap(&pm_info->iomuxc_base.vbase); 500 iomuxc_map_failed: 501 iounmap(&pm_info->src_base.vbase); 502 src_map_failed: 503 iounmap(&pm_info->mmdc_base.vbase); 504 put_node: 505 of_node_put(node); 506 507 return ret; 508 } 509 510 static void __init imx6_pm_common_init(const struct imx6_pm_socdata 511 *socdata) 512 { 513 struct regmap *gpr; 514 int ret; 515 516 WARN_ON(!ccm_base); 517 518 if (IS_ENABLED(CONFIG_SUSPEND)) { 519 ret = imx6q_suspend_init(socdata); 520 if (ret) 521 pr_warn("%s: No DDR LPM support with suspend %d!\n", 522 __func__, ret); 523 } 524 525 /* 526 * This is for SW workaround step #1 of ERR007265, see comments 527 * in imx6q_set_lpm for details of this errata. 528 * Force IOMUXC irq pending, so that the interrupt to GPC can be 529 * used to deassert dsm_request signal when the signal gets 530 * asserted unexpectedly. 531 */ 532 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 533 if (!IS_ERR(gpr)) 534 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, 535 IMX6Q_GPR1_GINT); 536 } 537 538 void __init imx6q_pm_init(void) 539 { 540 imx6_pm_common_init(&imx6q_pm_data); 541 } 542 543 void __init imx6dl_pm_init(void) 544 { 545 imx6_pm_common_init(&imx6dl_pm_data); 546 } 547 548 void __init imx6sl_pm_init(void) 549 { 550 imx6_pm_common_init(&imx6sl_pm_data); 551 } 552