19cdde721SShawn Guo /* 29cdde721SShawn Guo * Copyright 2011-2014 Freescale Semiconductor, Inc. 39cdde721SShawn Guo * Copyright 2011 Linaro Ltd. 49cdde721SShawn Guo * 59cdde721SShawn Guo * The code contained herein is licensed under the GNU General Public 69cdde721SShawn Guo * License. You may obtain a copy of the GNU General Public License 79cdde721SShawn Guo * Version 2 or later at the following locations: 89cdde721SShawn Guo * 99cdde721SShawn Guo * http://www.opensource.org/licenses/gpl-license.html 109cdde721SShawn Guo * http://www.gnu.org/copyleft/gpl.html 119cdde721SShawn Guo */ 129cdde721SShawn Guo 139cdde721SShawn Guo #include <linux/delay.h> 149cdde721SShawn Guo #include <linux/init.h> 159cdde721SShawn Guo #include <linux/io.h> 169cdde721SShawn Guo #include <linux/irq.h> 179cdde721SShawn Guo #include <linux/genalloc.h> 189cdde721SShawn Guo #include <linux/mfd/syscon.h> 199cdde721SShawn Guo #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 209cdde721SShawn Guo #include <linux/of.h> 219cdde721SShawn Guo #include <linux/of_address.h> 229cdde721SShawn Guo #include <linux/of_platform.h> 239cdde721SShawn Guo #include <linux/regmap.h> 249cdde721SShawn Guo #include <linux/suspend.h> 259cdde721SShawn Guo #include <asm/cacheflush.h> 269cdde721SShawn Guo #include <asm/fncpy.h> 279cdde721SShawn Guo #include <asm/proc-fns.h> 289cdde721SShawn Guo #include <asm/suspend.h> 299cdde721SShawn Guo #include <asm/tlb.h> 309cdde721SShawn Guo 319cdde721SShawn Guo #include "common.h" 329cdde721SShawn Guo #include "hardware.h" 339cdde721SShawn Guo 349cdde721SShawn Guo #define CCR 0x0 359cdde721SShawn Guo #define BM_CCR_WB_COUNT (0x7 << 16) 369cdde721SShawn Guo #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 379cdde721SShawn Guo #define BM_CCR_RBC_EN (0x1 << 27) 389cdde721SShawn Guo 399cdde721SShawn Guo #define CLPCR 0x54 409cdde721SShawn Guo #define BP_CLPCR_LPM 0 419cdde721SShawn Guo #define BM_CLPCR_LPM (0x3 << 0) 429cdde721SShawn Guo #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 439cdde721SShawn Guo #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 449cdde721SShawn Guo #define BM_CLPCR_SBYOS (0x1 << 6) 459cdde721SShawn Guo #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) 469cdde721SShawn Guo #define BM_CLPCR_VSTBY (0x1 << 8) 479cdde721SShawn Guo #define BP_CLPCR_STBY_COUNT 9 489cdde721SShawn Guo #define BM_CLPCR_STBY_COUNT (0x3 << 9) 499cdde721SShawn Guo #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) 509cdde721SShawn Guo #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) 519cdde721SShawn Guo #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) 529cdde721SShawn Guo #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) 539cdde721SShawn Guo #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) 549cdde721SShawn Guo #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) 559cdde721SShawn Guo #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) 569cdde721SShawn Guo #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) 579cdde721SShawn Guo #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) 589cdde721SShawn Guo #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 599cdde721SShawn Guo #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 609cdde721SShawn Guo 619cdde721SShawn Guo #define CGPR 0x64 629cdde721SShawn Guo #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) 639cdde721SShawn Guo 649cdde721SShawn Guo #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 659cdde721SShawn Guo #define MX6_MAX_MMDC_IO_NUM 33 669cdde721SShawn Guo 679cdde721SShawn Guo static void __iomem *ccm_base; 689cdde721SShawn Guo static void __iomem *suspend_ocram_base; 699cdde721SShawn Guo static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); 709cdde721SShawn Guo 719cdde721SShawn Guo /* 729cdde721SShawn Guo * suspend ocram space layout: 739cdde721SShawn Guo * ======================== high address ====================== 749cdde721SShawn Guo * . 759cdde721SShawn Guo * . 769cdde721SShawn Guo * . 779cdde721SShawn Guo * ^ 789cdde721SShawn Guo * ^ 799cdde721SShawn Guo * ^ 809cdde721SShawn Guo * imx6_suspend code 819cdde721SShawn Guo * PM_INFO structure(imx6_cpu_pm_info) 829cdde721SShawn Guo * ======================== low address ======================= 839cdde721SShawn Guo */ 849cdde721SShawn Guo 859cdde721SShawn Guo struct imx6_pm_base { 869cdde721SShawn Guo phys_addr_t pbase; 879cdde721SShawn Guo void __iomem *vbase; 889cdde721SShawn Guo }; 899cdde721SShawn Guo 909cdde721SShawn Guo struct imx6_pm_socdata { 919cdde721SShawn Guo u32 cpu_type; 929cdde721SShawn Guo const char *mmdc_compat; 939cdde721SShawn Guo const char *src_compat; 949cdde721SShawn Guo const char *iomuxc_compat; 959cdde721SShawn Guo const char *gpc_compat; 969cdde721SShawn Guo const u32 mmdc_io_num; 979cdde721SShawn Guo const u32 *mmdc_io_offset; 989cdde721SShawn Guo }; 999cdde721SShawn Guo 1009cdde721SShawn Guo static const u32 imx6q_mmdc_io_offset[] __initconst = { 1019cdde721SShawn Guo 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ 1029cdde721SShawn Guo 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ 1039cdde721SShawn Guo 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 1049cdde721SShawn Guo 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ 1059cdde721SShawn Guo 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ 1069cdde721SShawn Guo 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ 1079cdde721SShawn Guo 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 1089cdde721SShawn Guo 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ 1099cdde721SShawn Guo 0x74c, /* GPR_ADDS */ 1109cdde721SShawn Guo }; 1119cdde721SShawn Guo 1129cdde721SShawn Guo static const u32 imx6dl_mmdc_io_offset[] __initconst = { 1139cdde721SShawn Guo 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 1149cdde721SShawn Guo 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ 1159cdde721SShawn Guo 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 1169cdde721SShawn Guo 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ 1179cdde721SShawn Guo 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ 1189cdde721SShawn Guo 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ 1199cdde721SShawn Guo 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 1209cdde721SShawn Guo 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ 1219cdde721SShawn Guo 0x74c, /* GPR_ADDS */ 1229cdde721SShawn Guo }; 1239cdde721SShawn Guo 1249cdde721SShawn Guo static const u32 imx6sl_mmdc_io_offset[] __initconst = { 1259cdde721SShawn Guo 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ 1269cdde721SShawn Guo 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ 1279cdde721SShawn Guo 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 1289cdde721SShawn Guo 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ 1299cdde721SShawn Guo 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ 1309cdde721SShawn Guo }; 1319cdde721SShawn Guo 132ff843d62SAnson Huang static const u32 imx6sx_mmdc_io_offset[] __initconst = { 133ff843d62SAnson Huang 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 134ff843d62SAnson Huang 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ 135ff843d62SAnson Huang 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 136ff843d62SAnson Huang 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ 137ff843d62SAnson Huang 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ 138ff843d62SAnson Huang }; 139ff843d62SAnson Huang 1409cdde721SShawn Guo static const struct imx6_pm_socdata imx6q_pm_data __initconst = { 1419cdde721SShawn Guo .cpu_type = MXC_CPU_IMX6Q, 1429cdde721SShawn Guo .mmdc_compat = "fsl,imx6q-mmdc", 1439cdde721SShawn Guo .src_compat = "fsl,imx6q-src", 1449cdde721SShawn Guo .iomuxc_compat = "fsl,imx6q-iomuxc", 1459cdde721SShawn Guo .gpc_compat = "fsl,imx6q-gpc", 1469cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), 1479cdde721SShawn Guo .mmdc_io_offset = imx6q_mmdc_io_offset, 1489cdde721SShawn Guo }; 1499cdde721SShawn Guo 1509cdde721SShawn Guo static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 1519cdde721SShawn Guo .cpu_type = MXC_CPU_IMX6DL, 1529cdde721SShawn Guo .mmdc_compat = "fsl,imx6q-mmdc", 1539cdde721SShawn Guo .src_compat = "fsl,imx6q-src", 1549cdde721SShawn Guo .iomuxc_compat = "fsl,imx6dl-iomuxc", 1559cdde721SShawn Guo .gpc_compat = "fsl,imx6q-gpc", 1569cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), 1579cdde721SShawn Guo .mmdc_io_offset = imx6dl_mmdc_io_offset, 1589cdde721SShawn Guo }; 1599cdde721SShawn Guo 1609cdde721SShawn Guo static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 1619cdde721SShawn Guo .cpu_type = MXC_CPU_IMX6SL, 1629cdde721SShawn Guo .mmdc_compat = "fsl,imx6sl-mmdc", 1639cdde721SShawn Guo .src_compat = "fsl,imx6sl-src", 1649cdde721SShawn Guo .iomuxc_compat = "fsl,imx6sl-iomuxc", 1659cdde721SShawn Guo .gpc_compat = "fsl,imx6sl-gpc", 1669cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), 1679cdde721SShawn Guo .mmdc_io_offset = imx6sl_mmdc_io_offset, 1689cdde721SShawn Guo }; 1699cdde721SShawn Guo 170ff843d62SAnson Huang static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { 171ff843d62SAnson Huang .cpu_type = MXC_CPU_IMX6SX, 172ff843d62SAnson Huang .mmdc_compat = "fsl,imx6sx-mmdc", 173ff843d62SAnson Huang .src_compat = "fsl,imx6sx-src", 174ff843d62SAnson Huang .iomuxc_compat = "fsl,imx6sx-iomuxc", 175ff843d62SAnson Huang .gpc_compat = "fsl,imx6sx-gpc", 176ff843d62SAnson Huang .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), 177ff843d62SAnson Huang .mmdc_io_offset = imx6sx_mmdc_io_offset, 178ff843d62SAnson Huang }; 179ff843d62SAnson Huang 1809cdde721SShawn Guo /* 1819cdde721SShawn Guo * This structure is for passing necessary data for low level ocram 1829cdde721SShawn Guo * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct 1839cdde721SShawn Guo * definition is changed, the offset definition in 1849cdde721SShawn Guo * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, 1859cdde721SShawn Guo * otherwise, the suspend to ocram function will be broken! 1869cdde721SShawn Guo */ 1879cdde721SShawn Guo struct imx6_cpu_pm_info { 1889cdde721SShawn Guo phys_addr_t pbase; /* The physical address of pm_info. */ 1899cdde721SShawn Guo phys_addr_t resume_addr; /* The physical resume address for asm code */ 1909cdde721SShawn Guo u32 cpu_type; 1919cdde721SShawn Guo u32 pm_info_size; /* Size of pm_info. */ 1929cdde721SShawn Guo struct imx6_pm_base mmdc_base; 1939cdde721SShawn Guo struct imx6_pm_base src_base; 1949cdde721SShawn Guo struct imx6_pm_base iomuxc_base; 1959cdde721SShawn Guo struct imx6_pm_base ccm_base; 1969cdde721SShawn Guo struct imx6_pm_base gpc_base; 1979cdde721SShawn Guo struct imx6_pm_base l2_base; 1989cdde721SShawn Guo u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ 1999cdde721SShawn Guo u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ 2009cdde721SShawn Guo } __aligned(8); 2019cdde721SShawn Guo 2029cdde721SShawn Guo void imx6q_set_int_mem_clk_lpm(void) 2039cdde721SShawn Guo { 2049cdde721SShawn Guo u32 val = readl_relaxed(ccm_base + CGPR); 2059cdde721SShawn Guo 2069cdde721SShawn Guo val |= BM_CGPR_INT_MEM_CLK_LPM; 2079cdde721SShawn Guo writel_relaxed(val, ccm_base + CGPR); 2089cdde721SShawn Guo } 2099cdde721SShawn Guo 2109cdde721SShawn Guo static void imx6q_enable_rbc(bool enable) 2119cdde721SShawn Guo { 2129cdde721SShawn Guo u32 val; 2139cdde721SShawn Guo 2149cdde721SShawn Guo /* 2159cdde721SShawn Guo * need to mask all interrupts in GPC before 2169cdde721SShawn Guo * operating RBC configurations 2179cdde721SShawn Guo */ 2189cdde721SShawn Guo imx_gpc_mask_all(); 2199cdde721SShawn Guo 2209cdde721SShawn Guo /* configure RBC enable bit */ 2219cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2229cdde721SShawn Guo val &= ~BM_CCR_RBC_EN; 2239cdde721SShawn Guo val |= enable ? BM_CCR_RBC_EN : 0; 2249cdde721SShawn Guo writel_relaxed(val, ccm_base + CCR); 2259cdde721SShawn Guo 2269cdde721SShawn Guo /* configure RBC count */ 2279cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2289cdde721SShawn Guo val &= ~BM_CCR_RBC_BYPASS_COUNT; 2299cdde721SShawn Guo val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; 2309cdde721SShawn Guo writel(val, ccm_base + CCR); 2319cdde721SShawn Guo 2329cdde721SShawn Guo /* 2339cdde721SShawn Guo * need to delay at least 2 cycles of CKIL(32K) 2349cdde721SShawn Guo * due to hardware design requirement, which is 2359cdde721SShawn Guo * ~61us, here we use 65us for safe 2369cdde721SShawn Guo */ 2379cdde721SShawn Guo udelay(65); 2389cdde721SShawn Guo 2399cdde721SShawn Guo /* restore GPC interrupt mask settings */ 2409cdde721SShawn Guo imx_gpc_restore_all(); 2419cdde721SShawn Guo } 2429cdde721SShawn Guo 2439cdde721SShawn Guo static void imx6q_enable_wb(bool enable) 2449cdde721SShawn Guo { 2459cdde721SShawn Guo u32 val; 2469cdde721SShawn Guo 2479cdde721SShawn Guo /* configure well bias enable bit */ 2489cdde721SShawn Guo val = readl_relaxed(ccm_base + CLPCR); 2499cdde721SShawn Guo val &= ~BM_CLPCR_WB_PER_AT_LPM; 2509cdde721SShawn Guo val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; 2519cdde721SShawn Guo writel_relaxed(val, ccm_base + CLPCR); 2529cdde721SShawn Guo 2539cdde721SShawn Guo /* configure well bias count */ 2549cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2559cdde721SShawn Guo val &= ~BM_CCR_WB_COUNT; 2569cdde721SShawn Guo val |= enable ? BM_CCR_WB_COUNT : 0; 2579cdde721SShawn Guo writel_relaxed(val, ccm_base + CCR); 2589cdde721SShawn Guo } 2599cdde721SShawn Guo 2609cdde721SShawn Guo int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 2619cdde721SShawn Guo { 262ff050ad1SLinus Torvalds struct irq_data *iomuxc_irq_data = irq_get_irq_data(32); 2639cdde721SShawn Guo u32 val = readl_relaxed(ccm_base + CLPCR); 2649cdde721SShawn Guo 2659cdde721SShawn Guo val &= ~BM_CLPCR_LPM; 2669cdde721SShawn Guo switch (mode) { 2679cdde721SShawn Guo case WAIT_CLOCKED: 2689cdde721SShawn Guo break; 2699cdde721SShawn Guo case WAIT_UNCLOCKED: 2709cdde721SShawn Guo val |= 0x1 << BP_CLPCR_LPM; 2719cdde721SShawn Guo val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; 2729cdde721SShawn Guo break; 2739cdde721SShawn Guo case STOP_POWER_ON: 2749cdde721SShawn Guo val |= 0x2 << BP_CLPCR_LPM; 2759cdde721SShawn Guo break; 2769cdde721SShawn Guo case WAIT_UNCLOCKED_POWER_OFF: 2779cdde721SShawn Guo val |= 0x1 << BP_CLPCR_LPM; 2789cdde721SShawn Guo val &= ~BM_CLPCR_VSTBY; 2799cdde721SShawn Guo val &= ~BM_CLPCR_SBYOS; 2809cdde721SShawn Guo break; 2819cdde721SShawn Guo case STOP_POWER_OFF: 2829cdde721SShawn Guo val |= 0x2 << BP_CLPCR_LPM; 2839cdde721SShawn Guo val |= 0x3 << BP_CLPCR_STBY_COUNT; 2849cdde721SShawn Guo val |= BM_CLPCR_VSTBY; 2859cdde721SShawn Guo val |= BM_CLPCR_SBYOS; 286ff843d62SAnson Huang if (cpu_is_imx6sl()) 2879cdde721SShawn Guo val |= BM_CLPCR_BYPASS_PMIC_READY; 288ff843d62SAnson Huang if (cpu_is_imx6sl() || cpu_is_imx6sx()) 2899cdde721SShawn Guo val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 290ff843d62SAnson Huang else 2919cdde721SShawn Guo val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 2929cdde721SShawn Guo break; 2939cdde721SShawn Guo default: 2949cdde721SShawn Guo return -EINVAL; 2959cdde721SShawn Guo } 2969cdde721SShawn Guo 2979cdde721SShawn Guo /* 2989cdde721SShawn Guo * ERR007265: CCM: When improper low-power sequence is used, 2999cdde721SShawn Guo * the SoC enters low power mode before the ARM core executes WFI. 3009cdde721SShawn Guo * 3019cdde721SShawn Guo * Software workaround: 3029cdde721SShawn Guo * 1) Software should trigger IRQ #32 (IOMUX) to be always pending 3039cdde721SShawn Guo * by setting IOMUX_GPR1_GINT. 3049cdde721SShawn Guo * 2) Software should then unmask IRQ #32 in GPC before setting CCM 3059cdde721SShawn Guo * Low-Power mode. 3069cdde721SShawn Guo * 3) Software should mask IRQ #32 right after CCM Low-Power mode 3079cdde721SShawn Guo * is set (set bits 0-1 of CCM_CLPCR). 3089cdde721SShawn Guo */ 309ff050ad1SLinus Torvalds imx_gpc_irq_unmask(iomuxc_irq_data); 3109cdde721SShawn Guo writel_relaxed(val, ccm_base + CLPCR); 311ff050ad1SLinus Torvalds imx_gpc_irq_mask(iomuxc_irq_data); 3129cdde721SShawn Guo 3139cdde721SShawn Guo return 0; 3149cdde721SShawn Guo } 3159cdde721SShawn Guo 3169cdde721SShawn Guo static int imx6q_suspend_finish(unsigned long val) 3179cdde721SShawn Guo { 3189cdde721SShawn Guo if (!imx6_suspend_in_ocram_fn) { 3199cdde721SShawn Guo cpu_do_idle(); 3209cdde721SShawn Guo } else { 3219cdde721SShawn Guo /* 3229cdde721SShawn Guo * call low level suspend function in ocram, 3239cdde721SShawn Guo * as we need to float DDR IO. 3249cdde721SShawn Guo */ 3259cdde721SShawn Guo local_flush_tlb_all(); 3269cdde721SShawn Guo imx6_suspend_in_ocram_fn(suspend_ocram_base); 3279cdde721SShawn Guo } 3289cdde721SShawn Guo 3299cdde721SShawn Guo return 0; 3309cdde721SShawn Guo } 3319cdde721SShawn Guo 3329cdde721SShawn Guo static int imx6q_pm_enter(suspend_state_t state) 3339cdde721SShawn Guo { 3349cdde721SShawn Guo switch (state) { 3359cdde721SShawn Guo case PM_SUSPEND_MEM: 3369cdde721SShawn Guo imx6q_set_lpm(STOP_POWER_OFF); 3379cdde721SShawn Guo imx6q_enable_wb(true); 3389cdde721SShawn Guo /* 3399cdde721SShawn Guo * For suspend into ocram, asm code already take care of 3409cdde721SShawn Guo * RBC setting, so we do NOT need to do that here. 3419cdde721SShawn Guo */ 3429cdde721SShawn Guo if (!imx6_suspend_in_ocram_fn) 3439cdde721SShawn Guo imx6q_enable_rbc(true); 3449cdde721SShawn Guo imx_gpc_pre_suspend(); 3459cdde721SShawn Guo imx_anatop_pre_suspend(); 3469cdde721SShawn Guo imx_set_cpu_jump(0, v7_cpu_resume); 3479cdde721SShawn Guo /* Zzz ... */ 3489cdde721SShawn Guo cpu_suspend(0, imx6q_suspend_finish); 3499cdde721SShawn Guo if (cpu_is_imx6q() || cpu_is_imx6dl()) 3509cdde721SShawn Guo imx_smp_prepare(); 3519cdde721SShawn Guo imx_anatop_post_resume(); 3529cdde721SShawn Guo imx_gpc_post_resume(); 3539cdde721SShawn Guo imx6q_enable_rbc(false); 3549cdde721SShawn Guo imx6q_enable_wb(false); 3559cdde721SShawn Guo imx6q_set_lpm(WAIT_CLOCKED); 3569cdde721SShawn Guo break; 3579cdde721SShawn Guo default: 3589cdde721SShawn Guo return -EINVAL; 3599cdde721SShawn Guo } 3609cdde721SShawn Guo 3619cdde721SShawn Guo return 0; 3629cdde721SShawn Guo } 3639cdde721SShawn Guo 3649cdde721SShawn Guo static const struct platform_suspend_ops imx6q_pm_ops = { 3659cdde721SShawn Guo .enter = imx6q_pm_enter, 3669cdde721SShawn Guo .valid = suspend_valid_only_mem, 3679cdde721SShawn Guo }; 3689cdde721SShawn Guo 3699cdde721SShawn Guo void __init imx6q_pm_set_ccm_base(void __iomem *base) 3709cdde721SShawn Guo { 3719cdde721SShawn Guo ccm_base = base; 3729cdde721SShawn Guo } 3739cdde721SShawn Guo 3749cdde721SShawn Guo static int __init imx6_pm_get_base(struct imx6_pm_base *base, 3759cdde721SShawn Guo const char *compat) 3769cdde721SShawn Guo { 3779cdde721SShawn Guo struct device_node *node; 3789cdde721SShawn Guo struct resource res; 3799cdde721SShawn Guo int ret = 0; 3809cdde721SShawn Guo 3819cdde721SShawn Guo node = of_find_compatible_node(NULL, NULL, compat); 3829cdde721SShawn Guo if (!node) { 3839cdde721SShawn Guo ret = -ENODEV; 3849cdde721SShawn Guo goto out; 3859cdde721SShawn Guo } 3869cdde721SShawn Guo 3879cdde721SShawn Guo ret = of_address_to_resource(node, 0, &res); 3889cdde721SShawn Guo if (ret) 3899cdde721SShawn Guo goto put_node; 3909cdde721SShawn Guo 3919cdde721SShawn Guo base->pbase = res.start; 3929cdde721SShawn Guo base->vbase = ioremap(res.start, resource_size(&res)); 3939cdde721SShawn Guo if (!base->vbase) 3949cdde721SShawn Guo ret = -ENOMEM; 3959cdde721SShawn Guo 3969cdde721SShawn Guo put_node: 3979cdde721SShawn Guo of_node_put(node); 3989cdde721SShawn Guo out: 3999cdde721SShawn Guo return ret; 4009cdde721SShawn Guo } 4019cdde721SShawn Guo 4029cdde721SShawn Guo static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) 4039cdde721SShawn Guo { 4049cdde721SShawn Guo phys_addr_t ocram_pbase; 4059cdde721SShawn Guo struct device_node *node; 4069cdde721SShawn Guo struct platform_device *pdev; 4079cdde721SShawn Guo struct imx6_cpu_pm_info *pm_info; 4089cdde721SShawn Guo struct gen_pool *ocram_pool; 4099cdde721SShawn Guo unsigned long ocram_base; 4109cdde721SShawn Guo int i, ret = 0; 4119cdde721SShawn Guo const u32 *mmdc_offset_array; 4129cdde721SShawn Guo 4139cdde721SShawn Guo suspend_set_ops(&imx6q_pm_ops); 4149cdde721SShawn Guo 4159cdde721SShawn Guo if (!socdata) { 4169cdde721SShawn Guo pr_warn("%s: invalid argument!\n", __func__); 4179cdde721SShawn Guo return -EINVAL; 4189cdde721SShawn Guo } 4199cdde721SShawn Guo 4209cdde721SShawn Guo node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 4219cdde721SShawn Guo if (!node) { 4229cdde721SShawn Guo pr_warn("%s: failed to find ocram node!\n", __func__); 4239cdde721SShawn Guo return -ENODEV; 4249cdde721SShawn Guo } 4259cdde721SShawn Guo 4269cdde721SShawn Guo pdev = of_find_device_by_node(node); 4279cdde721SShawn Guo if (!pdev) { 4289cdde721SShawn Guo pr_warn("%s: failed to find ocram device!\n", __func__); 4299cdde721SShawn Guo ret = -ENODEV; 4309cdde721SShawn Guo goto put_node; 4319cdde721SShawn Guo } 4329cdde721SShawn Guo 4339cdde721SShawn Guo ocram_pool = dev_get_gen_pool(&pdev->dev); 4349cdde721SShawn Guo if (!ocram_pool) { 4359cdde721SShawn Guo pr_warn("%s: ocram pool unavailable!\n", __func__); 4369cdde721SShawn Guo ret = -ENODEV; 4379cdde721SShawn Guo goto put_node; 4389cdde721SShawn Guo } 4399cdde721SShawn Guo 4409cdde721SShawn Guo ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); 4419cdde721SShawn Guo if (!ocram_base) { 4429cdde721SShawn Guo pr_warn("%s: unable to alloc ocram!\n", __func__); 4439cdde721SShawn Guo ret = -ENOMEM; 4449cdde721SShawn Guo goto put_node; 4459cdde721SShawn Guo } 4469cdde721SShawn Guo 4479cdde721SShawn Guo ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); 4489cdde721SShawn Guo 4499cdde721SShawn Guo suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, 4509cdde721SShawn Guo MX6Q_SUSPEND_OCRAM_SIZE, false); 4519cdde721SShawn Guo 4529cdde721SShawn Guo pm_info = suspend_ocram_base; 4539cdde721SShawn Guo pm_info->pbase = ocram_pbase; 4549cdde721SShawn Guo pm_info->resume_addr = virt_to_phys(v7_cpu_resume); 4559cdde721SShawn Guo pm_info->pm_info_size = sizeof(*pm_info); 4569cdde721SShawn Guo 4579cdde721SShawn Guo /* 4589cdde721SShawn Guo * ccm physical address is not used by asm code currently, 4599cdde721SShawn Guo * so get ccm virtual address directly, as we already have 4609cdde721SShawn Guo * it from ccm driver. 4619cdde721SShawn Guo */ 4629cdde721SShawn Guo pm_info->ccm_base.vbase = ccm_base; 4639cdde721SShawn Guo 4649cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); 4659cdde721SShawn Guo if (ret) { 4669cdde721SShawn Guo pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); 4679cdde721SShawn Guo goto put_node; 4689cdde721SShawn Guo } 4699cdde721SShawn Guo 4709cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); 4719cdde721SShawn Guo if (ret) { 4729cdde721SShawn Guo pr_warn("%s: failed to get src base %d!\n", __func__, ret); 4739cdde721SShawn Guo goto src_map_failed; 4749cdde721SShawn Guo } 4759cdde721SShawn Guo 4769cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); 4779cdde721SShawn Guo if (ret) { 4789cdde721SShawn Guo pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); 4799cdde721SShawn Guo goto iomuxc_map_failed; 4809cdde721SShawn Guo } 4819cdde721SShawn Guo 4829cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); 4839cdde721SShawn Guo if (ret) { 4849cdde721SShawn Guo pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); 4859cdde721SShawn Guo goto gpc_map_failed; 4869cdde721SShawn Guo } 4879cdde721SShawn Guo 4889cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache"); 4899cdde721SShawn Guo if (ret) { 4909cdde721SShawn Guo pr_warn("%s: failed to get pl310-cache base %d!\n", 4919cdde721SShawn Guo __func__, ret); 4929cdde721SShawn Guo goto pl310_cache_map_failed; 4939cdde721SShawn Guo } 4949cdde721SShawn Guo 4959cdde721SShawn Guo pm_info->cpu_type = socdata->cpu_type; 4969cdde721SShawn Guo pm_info->mmdc_io_num = socdata->mmdc_io_num; 4979cdde721SShawn Guo mmdc_offset_array = socdata->mmdc_io_offset; 4989cdde721SShawn Guo 4999cdde721SShawn Guo for (i = 0; i < pm_info->mmdc_io_num; i++) { 5009cdde721SShawn Guo pm_info->mmdc_io_val[i][0] = 5019cdde721SShawn Guo mmdc_offset_array[i]; 5029cdde721SShawn Guo pm_info->mmdc_io_val[i][1] = 5039cdde721SShawn Guo readl_relaxed(pm_info->iomuxc_base.vbase + 5049cdde721SShawn Guo mmdc_offset_array[i]); 5059cdde721SShawn Guo } 5069cdde721SShawn Guo 5079cdde721SShawn Guo imx6_suspend_in_ocram_fn = fncpy( 5089cdde721SShawn Guo suspend_ocram_base + sizeof(*pm_info), 5099cdde721SShawn Guo &imx6_suspend, 5109cdde721SShawn Guo MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); 5119cdde721SShawn Guo 5129cdde721SShawn Guo goto put_node; 5139cdde721SShawn Guo 5149cdde721SShawn Guo pl310_cache_map_failed: 5159cdde721SShawn Guo iounmap(&pm_info->gpc_base.vbase); 5169cdde721SShawn Guo gpc_map_failed: 5179cdde721SShawn Guo iounmap(&pm_info->iomuxc_base.vbase); 5189cdde721SShawn Guo iomuxc_map_failed: 5199cdde721SShawn Guo iounmap(&pm_info->src_base.vbase); 5209cdde721SShawn Guo src_map_failed: 5219cdde721SShawn Guo iounmap(&pm_info->mmdc_base.vbase); 5229cdde721SShawn Guo put_node: 5239cdde721SShawn Guo of_node_put(node); 5249cdde721SShawn Guo 5259cdde721SShawn Guo return ret; 5269cdde721SShawn Guo } 5279cdde721SShawn Guo 5289cdde721SShawn Guo static void __init imx6_pm_common_init(const struct imx6_pm_socdata 5299cdde721SShawn Guo *socdata) 5309cdde721SShawn Guo { 5319cdde721SShawn Guo struct regmap *gpr; 5329cdde721SShawn Guo int ret; 5339cdde721SShawn Guo 5349cdde721SShawn Guo WARN_ON(!ccm_base); 5359cdde721SShawn Guo 5369cdde721SShawn Guo if (IS_ENABLED(CONFIG_SUSPEND)) { 5379cdde721SShawn Guo ret = imx6q_suspend_init(socdata); 5389cdde721SShawn Guo if (ret) 5399cdde721SShawn Guo pr_warn("%s: No DDR LPM support with suspend %d!\n", 5409cdde721SShawn Guo __func__, ret); 5419cdde721SShawn Guo } 5429cdde721SShawn Guo 5439cdde721SShawn Guo /* 5449cdde721SShawn Guo * This is for SW workaround step #1 of ERR007265, see comments 5459cdde721SShawn Guo * in imx6q_set_lpm for details of this errata. 5469cdde721SShawn Guo * Force IOMUXC irq pending, so that the interrupt to GPC can be 5479cdde721SShawn Guo * used to deassert dsm_request signal when the signal gets 5489cdde721SShawn Guo * asserted unexpectedly. 5499cdde721SShawn Guo */ 5509cdde721SShawn Guo gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 5519cdde721SShawn Guo if (!IS_ERR(gpr)) 5529cdde721SShawn Guo regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, 5539cdde721SShawn Guo IMX6Q_GPR1_GINT); 5549cdde721SShawn Guo } 5559cdde721SShawn Guo 5569cdde721SShawn Guo void __init imx6q_pm_init(void) 5579cdde721SShawn Guo { 5589cdde721SShawn Guo imx6_pm_common_init(&imx6q_pm_data); 5599cdde721SShawn Guo } 5609cdde721SShawn Guo 5619cdde721SShawn Guo void __init imx6dl_pm_init(void) 5629cdde721SShawn Guo { 5639cdde721SShawn Guo imx6_pm_common_init(&imx6dl_pm_data); 5649cdde721SShawn Guo } 5659cdde721SShawn Guo 5669cdde721SShawn Guo void __init imx6sl_pm_init(void) 5679cdde721SShawn Guo { 5689cdde721SShawn Guo imx6_pm_common_init(&imx6sl_pm_data); 5699cdde721SShawn Guo } 570ff843d62SAnson Huang 571ff843d62SAnson Huang void __init imx6sx_pm_init(void) 572ff843d62SAnson Huang { 573ff843d62SAnson Huang imx6_pm_common_init(&imx6sx_pm_data); 574ff843d62SAnson Huang } 575