19cdde721SShawn Guo /* 29cdde721SShawn Guo * Copyright 2011-2014 Freescale Semiconductor, Inc. 39cdde721SShawn Guo * Copyright 2011 Linaro Ltd. 49cdde721SShawn Guo * 59cdde721SShawn Guo * The code contained herein is licensed under the GNU General Public 69cdde721SShawn Guo * License. You may obtain a copy of the GNU General Public License 79cdde721SShawn Guo * Version 2 or later at the following locations: 89cdde721SShawn Guo * 99cdde721SShawn Guo * http://www.opensource.org/licenses/gpl-license.html 109cdde721SShawn Guo * http://www.gnu.org/copyleft/gpl.html 119cdde721SShawn Guo */ 129cdde721SShawn Guo 139cdde721SShawn Guo #include <linux/delay.h> 149cdde721SShawn Guo #include <linux/init.h> 159cdde721SShawn Guo #include <linux/io.h> 169cdde721SShawn Guo #include <linux/irq.h> 179cdde721SShawn Guo #include <linux/genalloc.h> 189cdde721SShawn Guo #include <linux/mfd/syscon.h> 199cdde721SShawn Guo #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 209cdde721SShawn Guo #include <linux/of.h> 219cdde721SShawn Guo #include <linux/of_address.h> 229cdde721SShawn Guo #include <linux/of_platform.h> 239cdde721SShawn Guo #include <linux/regmap.h> 249cdde721SShawn Guo #include <linux/suspend.h> 259cdde721SShawn Guo #include <asm/cacheflush.h> 269cdde721SShawn Guo #include <asm/fncpy.h> 279cdde721SShawn Guo #include <asm/proc-fns.h> 289cdde721SShawn Guo #include <asm/suspend.h> 299cdde721SShawn Guo #include <asm/tlb.h> 309cdde721SShawn Guo 319cdde721SShawn Guo #include "common.h" 329cdde721SShawn Guo #include "hardware.h" 339cdde721SShawn Guo 349cdde721SShawn Guo #define CCR 0x0 359cdde721SShawn Guo #define BM_CCR_WB_COUNT (0x7 << 16) 369cdde721SShawn Guo #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) 379cdde721SShawn Guo #define BM_CCR_RBC_EN (0x1 << 27) 389cdde721SShawn Guo 399cdde721SShawn Guo #define CLPCR 0x54 409cdde721SShawn Guo #define BP_CLPCR_LPM 0 419cdde721SShawn Guo #define BM_CLPCR_LPM (0x3 << 0) 429cdde721SShawn Guo #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) 439cdde721SShawn Guo #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 449cdde721SShawn Guo #define BM_CLPCR_SBYOS (0x1 << 6) 459cdde721SShawn Guo #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) 469cdde721SShawn Guo #define BM_CLPCR_VSTBY (0x1 << 8) 479cdde721SShawn Guo #define BP_CLPCR_STBY_COUNT 9 489cdde721SShawn Guo #define BM_CLPCR_STBY_COUNT (0x3 << 9) 499cdde721SShawn Guo #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) 509cdde721SShawn Guo #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) 519cdde721SShawn Guo #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) 529cdde721SShawn Guo #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) 539cdde721SShawn Guo #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) 549cdde721SShawn Guo #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) 559cdde721SShawn Guo #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) 569cdde721SShawn Guo #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) 579cdde721SShawn Guo #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) 589cdde721SShawn Guo #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 599cdde721SShawn Guo #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 609cdde721SShawn Guo 619cdde721SShawn Guo #define CGPR 0x64 629cdde721SShawn Guo #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) 639cdde721SShawn Guo 649cdde721SShawn Guo #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 659cdde721SShawn Guo #define MX6_MAX_MMDC_IO_NUM 33 669cdde721SShawn Guo 679cdde721SShawn Guo static void __iomem *ccm_base; 689cdde721SShawn Guo static void __iomem *suspend_ocram_base; 699cdde721SShawn Guo static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); 709cdde721SShawn Guo 719cdde721SShawn Guo /* 729cdde721SShawn Guo * suspend ocram space layout: 739cdde721SShawn Guo * ======================== high address ====================== 749cdde721SShawn Guo * . 759cdde721SShawn Guo * . 769cdde721SShawn Guo * . 779cdde721SShawn Guo * ^ 789cdde721SShawn Guo * ^ 799cdde721SShawn Guo * ^ 809cdde721SShawn Guo * imx6_suspend code 819cdde721SShawn Guo * PM_INFO structure(imx6_cpu_pm_info) 829cdde721SShawn Guo * ======================== low address ======================= 839cdde721SShawn Guo */ 849cdde721SShawn Guo 859cdde721SShawn Guo struct imx6_pm_base { 869cdde721SShawn Guo phys_addr_t pbase; 879cdde721SShawn Guo void __iomem *vbase; 889cdde721SShawn Guo }; 899cdde721SShawn Guo 909cdde721SShawn Guo struct imx6_pm_socdata { 91ec336b28SAnson Huang u32 ddr_type; 929cdde721SShawn Guo const char *mmdc_compat; 939cdde721SShawn Guo const char *src_compat; 949cdde721SShawn Guo const char *iomuxc_compat; 959cdde721SShawn Guo const char *gpc_compat; 96ee4a5f83SAnson Huang const char *pl310_compat; 979cdde721SShawn Guo const u32 mmdc_io_num; 989cdde721SShawn Guo const u32 *mmdc_io_offset; 999cdde721SShawn Guo }; 1009cdde721SShawn Guo 1019cdde721SShawn Guo static const u32 imx6q_mmdc_io_offset[] __initconst = { 1029cdde721SShawn Guo 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ 1039cdde721SShawn Guo 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ 1049cdde721SShawn Guo 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 1059cdde721SShawn Guo 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ 1069cdde721SShawn Guo 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ 1079cdde721SShawn Guo 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ 1089cdde721SShawn Guo 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 1099cdde721SShawn Guo 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ 1109cdde721SShawn Guo 0x74c, /* GPR_ADDS */ 1119cdde721SShawn Guo }; 1129cdde721SShawn Guo 1139cdde721SShawn Guo static const u32 imx6dl_mmdc_io_offset[] __initconst = { 1149cdde721SShawn Guo 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 1159cdde721SShawn Guo 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ 1169cdde721SShawn Guo 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ 1179cdde721SShawn Guo 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ 1189cdde721SShawn Guo 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ 1199cdde721SShawn Guo 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ 1209cdde721SShawn Guo 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ 1219cdde721SShawn Guo 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ 1229cdde721SShawn Guo 0x74c, /* GPR_ADDS */ 1239cdde721SShawn Guo }; 1249cdde721SShawn Guo 1259cdde721SShawn Guo static const u32 imx6sl_mmdc_io_offset[] __initconst = { 1269cdde721SShawn Guo 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ 1279cdde721SShawn Guo 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ 1289cdde721SShawn Guo 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 1299cdde721SShawn Guo 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ 1309cdde721SShawn Guo 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ 1319cdde721SShawn Guo }; 1329cdde721SShawn Guo 13322021948SAnson Huang static const u32 imx6sll_mmdc_io_offset[] __initconst = { 13422021948SAnson Huang 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ 13522021948SAnson Huang 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ 13622021948SAnson Huang 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ 13722021948SAnson Huang 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ 13822021948SAnson Huang }; 13922021948SAnson Huang 140ff843d62SAnson Huang static const u32 imx6sx_mmdc_io_offset[] __initconst = { 141ff843d62SAnson Huang 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 142ff843d62SAnson Huang 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ 143ff843d62SAnson Huang 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ 144ff843d62SAnson Huang 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ 145ff843d62SAnson Huang 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ 146ff843d62SAnson Huang }; 147ff843d62SAnson Huang 148ee4a5f83SAnson Huang static const u32 imx6ul_mmdc_io_offset[] __initconst = { 149ee4a5f83SAnson Huang 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ 150ee4a5f83SAnson Huang 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ 151ee4a5f83SAnson Huang 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ 152ee4a5f83SAnson Huang 0x494, 0x4b0, /* MODE_CTL, MODE, */ 153ee4a5f83SAnson Huang }; 154ee4a5f83SAnson Huang 1559cdde721SShawn Guo static const struct imx6_pm_socdata imx6q_pm_data __initconst = { 1569cdde721SShawn Guo .mmdc_compat = "fsl,imx6q-mmdc", 1579cdde721SShawn Guo .src_compat = "fsl,imx6q-src", 1589cdde721SShawn Guo .iomuxc_compat = "fsl,imx6q-iomuxc", 1599cdde721SShawn Guo .gpc_compat = "fsl,imx6q-gpc", 160ee4a5f83SAnson Huang .pl310_compat = "arm,pl310-cache", 1619cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), 1629cdde721SShawn Guo .mmdc_io_offset = imx6q_mmdc_io_offset, 1639cdde721SShawn Guo }; 1649cdde721SShawn Guo 1659cdde721SShawn Guo static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { 1669cdde721SShawn Guo .mmdc_compat = "fsl,imx6q-mmdc", 1679cdde721SShawn Guo .src_compat = "fsl,imx6q-src", 1689cdde721SShawn Guo .iomuxc_compat = "fsl,imx6dl-iomuxc", 1699cdde721SShawn Guo .gpc_compat = "fsl,imx6q-gpc", 170ee4a5f83SAnson Huang .pl310_compat = "arm,pl310-cache", 1719cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), 1729cdde721SShawn Guo .mmdc_io_offset = imx6dl_mmdc_io_offset, 1739cdde721SShawn Guo }; 1749cdde721SShawn Guo 1759cdde721SShawn Guo static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { 1769cdde721SShawn Guo .mmdc_compat = "fsl,imx6sl-mmdc", 1779cdde721SShawn Guo .src_compat = "fsl,imx6sl-src", 1789cdde721SShawn Guo .iomuxc_compat = "fsl,imx6sl-iomuxc", 1799cdde721SShawn Guo .gpc_compat = "fsl,imx6sl-gpc", 180ee4a5f83SAnson Huang .pl310_compat = "arm,pl310-cache", 1819cdde721SShawn Guo .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), 1829cdde721SShawn Guo .mmdc_io_offset = imx6sl_mmdc_io_offset, 1839cdde721SShawn Guo }; 1849cdde721SShawn Guo 18522021948SAnson Huang static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { 18622021948SAnson Huang .mmdc_compat = "fsl,imx6sll-mmdc", 18722021948SAnson Huang .src_compat = "fsl,imx6sll-src", 18822021948SAnson Huang .iomuxc_compat = "fsl,imx6sll-iomuxc", 18922021948SAnson Huang .gpc_compat = "fsl,imx6sll-gpc", 19022021948SAnson Huang .pl310_compat = "arm,pl310-cache", 19122021948SAnson Huang .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), 19222021948SAnson Huang .mmdc_io_offset = imx6sll_mmdc_io_offset, 19322021948SAnson Huang }; 19422021948SAnson Huang 195ff843d62SAnson Huang static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { 196ff843d62SAnson Huang .mmdc_compat = "fsl,imx6sx-mmdc", 197ff843d62SAnson Huang .src_compat = "fsl,imx6sx-src", 198ff843d62SAnson Huang .iomuxc_compat = "fsl,imx6sx-iomuxc", 199ff843d62SAnson Huang .gpc_compat = "fsl,imx6sx-gpc", 200ee4a5f83SAnson Huang .pl310_compat = "arm,pl310-cache", 201ff843d62SAnson Huang .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), 202ff843d62SAnson Huang .mmdc_io_offset = imx6sx_mmdc_io_offset, 203ff843d62SAnson Huang }; 204ff843d62SAnson Huang 205ee4a5f83SAnson Huang static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { 206ee4a5f83SAnson Huang .mmdc_compat = "fsl,imx6ul-mmdc", 207ee4a5f83SAnson Huang .src_compat = "fsl,imx6ul-src", 208ee4a5f83SAnson Huang .iomuxc_compat = "fsl,imx6ul-iomuxc", 209ee4a5f83SAnson Huang .gpc_compat = "fsl,imx6ul-gpc", 210ee4a5f83SAnson Huang .pl310_compat = NULL, 211ee4a5f83SAnson Huang .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), 212ee4a5f83SAnson Huang .mmdc_io_offset = imx6ul_mmdc_io_offset, 213ee4a5f83SAnson Huang }; 214ee4a5f83SAnson Huang 2159cdde721SShawn Guo /* 2169cdde721SShawn Guo * This structure is for passing necessary data for low level ocram 2179cdde721SShawn Guo * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct 2189cdde721SShawn Guo * definition is changed, the offset definition in 2199cdde721SShawn Guo * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, 2209cdde721SShawn Guo * otherwise, the suspend to ocram function will be broken! 2219cdde721SShawn Guo */ 2229cdde721SShawn Guo struct imx6_cpu_pm_info { 2239cdde721SShawn Guo phys_addr_t pbase; /* The physical address of pm_info. */ 2249cdde721SShawn Guo phys_addr_t resume_addr; /* The physical resume address for asm code */ 225ec336b28SAnson Huang u32 ddr_type; 2269cdde721SShawn Guo u32 pm_info_size; /* Size of pm_info. */ 2279cdde721SShawn Guo struct imx6_pm_base mmdc_base; 2289cdde721SShawn Guo struct imx6_pm_base src_base; 2299cdde721SShawn Guo struct imx6_pm_base iomuxc_base; 2309cdde721SShawn Guo struct imx6_pm_base ccm_base; 2319cdde721SShawn Guo struct imx6_pm_base gpc_base; 2329cdde721SShawn Guo struct imx6_pm_base l2_base; 2339cdde721SShawn Guo u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ 2349cdde721SShawn Guo u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ 2359cdde721SShawn Guo } __aligned(8); 2369cdde721SShawn Guo 2378765caa5SAnson Huang void imx6_set_int_mem_clk_lpm(bool enable) 2389cdde721SShawn Guo { 2399cdde721SShawn Guo u32 val = readl_relaxed(ccm_base + CGPR); 2409cdde721SShawn Guo 241dfea953aSAnson Huang val &= ~BM_CGPR_INT_MEM_CLK_LPM; 242dfea953aSAnson Huang if (enable) 2439cdde721SShawn Guo val |= BM_CGPR_INT_MEM_CLK_LPM; 2449cdde721SShawn Guo writel_relaxed(val, ccm_base + CGPR); 2459cdde721SShawn Guo } 2469cdde721SShawn Guo 24705136f08SAnson Huang void imx6_enable_rbc(bool enable) 2489cdde721SShawn Guo { 2499cdde721SShawn Guo u32 val; 2509cdde721SShawn Guo 2519cdde721SShawn Guo /* 2529cdde721SShawn Guo * need to mask all interrupts in GPC before 2539cdde721SShawn Guo * operating RBC configurations 2549cdde721SShawn Guo */ 2559cdde721SShawn Guo imx_gpc_mask_all(); 2569cdde721SShawn Guo 2579cdde721SShawn Guo /* configure RBC enable bit */ 2589cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2599cdde721SShawn Guo val &= ~BM_CCR_RBC_EN; 2609cdde721SShawn Guo val |= enable ? BM_CCR_RBC_EN : 0; 2619cdde721SShawn Guo writel_relaxed(val, ccm_base + CCR); 2629cdde721SShawn Guo 2639cdde721SShawn Guo /* configure RBC count */ 2649cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2659cdde721SShawn Guo val &= ~BM_CCR_RBC_BYPASS_COUNT; 2669cdde721SShawn Guo val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; 2679cdde721SShawn Guo writel(val, ccm_base + CCR); 2689cdde721SShawn Guo 2699cdde721SShawn Guo /* 2709cdde721SShawn Guo * need to delay at least 2 cycles of CKIL(32K) 2719cdde721SShawn Guo * due to hardware design requirement, which is 2729cdde721SShawn Guo * ~61us, here we use 65us for safe 2739cdde721SShawn Guo */ 2749cdde721SShawn Guo udelay(65); 2759cdde721SShawn Guo 2769cdde721SShawn Guo /* restore GPC interrupt mask settings */ 2779cdde721SShawn Guo imx_gpc_restore_all(); 2789cdde721SShawn Guo } 2799cdde721SShawn Guo 2809cdde721SShawn Guo static void imx6q_enable_wb(bool enable) 2819cdde721SShawn Guo { 2829cdde721SShawn Guo u32 val; 2839cdde721SShawn Guo 2849cdde721SShawn Guo /* configure well bias enable bit */ 2859cdde721SShawn Guo val = readl_relaxed(ccm_base + CLPCR); 2869cdde721SShawn Guo val &= ~BM_CLPCR_WB_PER_AT_LPM; 2879cdde721SShawn Guo val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; 2889cdde721SShawn Guo writel_relaxed(val, ccm_base + CLPCR); 2899cdde721SShawn Guo 2909cdde721SShawn Guo /* configure well bias count */ 2919cdde721SShawn Guo val = readl_relaxed(ccm_base + CCR); 2929cdde721SShawn Guo val &= ~BM_CCR_WB_COUNT; 2939cdde721SShawn Guo val |= enable ? BM_CCR_WB_COUNT : 0; 2949cdde721SShawn Guo writel_relaxed(val, ccm_base + CCR); 2959cdde721SShawn Guo } 2969cdde721SShawn Guo 2978fb76a07SShawn Guo int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 2989cdde721SShawn Guo { 2999cdde721SShawn Guo u32 val = readl_relaxed(ccm_base + CLPCR); 3009cdde721SShawn Guo 3019cdde721SShawn Guo val &= ~BM_CLPCR_LPM; 3029cdde721SShawn Guo switch (mode) { 3039cdde721SShawn Guo case WAIT_CLOCKED: 3049cdde721SShawn Guo break; 3059cdde721SShawn Guo case WAIT_UNCLOCKED: 3069cdde721SShawn Guo val |= 0x1 << BP_CLPCR_LPM; 3079cdde721SShawn Guo val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; 3089cdde721SShawn Guo break; 3099cdde721SShawn Guo case STOP_POWER_ON: 3109cdde721SShawn Guo val |= 0x2 << BP_CLPCR_LPM; 31180c0ecdcSAnson Huang val &= ~BM_CLPCR_VSTBY; 31280c0ecdcSAnson Huang val &= ~BM_CLPCR_SBYOS; 31380c0ecdcSAnson Huang if (cpu_is_imx6sl()) 31480c0ecdcSAnson Huang val |= BM_CLPCR_BYPASS_PMIC_READY; 315bf5a01d7SLeonard Crestez if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || 31607c4be9dSAnson Huang cpu_is_imx6ull() || cpu_is_imx6sll()) 31780c0ecdcSAnson Huang val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 31880c0ecdcSAnson Huang else 31980c0ecdcSAnson Huang val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 3209cdde721SShawn Guo break; 3219cdde721SShawn Guo case WAIT_UNCLOCKED_POWER_OFF: 3229cdde721SShawn Guo val |= 0x1 << BP_CLPCR_LPM; 3239cdde721SShawn Guo val &= ~BM_CLPCR_VSTBY; 3249cdde721SShawn Guo val &= ~BM_CLPCR_SBYOS; 3259cdde721SShawn Guo break; 3269cdde721SShawn Guo case STOP_POWER_OFF: 3279cdde721SShawn Guo val |= 0x2 << BP_CLPCR_LPM; 3289cdde721SShawn Guo val |= 0x3 << BP_CLPCR_STBY_COUNT; 3299cdde721SShawn Guo val |= BM_CLPCR_VSTBY; 3309cdde721SShawn Guo val |= BM_CLPCR_SBYOS; 3318aade778SAnson Huang if (cpu_is_imx6sl() || cpu_is_imx6sx()) 3329cdde721SShawn Guo val |= BM_CLPCR_BYPASS_PMIC_READY; 333bf5a01d7SLeonard Crestez if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || 33422021948SAnson Huang cpu_is_imx6ull() || cpu_is_imx6sll()) 3359cdde721SShawn Guo val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; 336ff843d62SAnson Huang else 3379cdde721SShawn Guo val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; 3389cdde721SShawn Guo break; 3399cdde721SShawn Guo default: 3409cdde721SShawn Guo return -EINVAL; 3419cdde721SShawn Guo } 3429cdde721SShawn Guo 3439cdde721SShawn Guo /* 3449cdde721SShawn Guo * ERR007265: CCM: When improper low-power sequence is used, 3459cdde721SShawn Guo * the SoC enters low power mode before the ARM core executes WFI. 3469cdde721SShawn Guo * 3479cdde721SShawn Guo * Software workaround: 3489cdde721SShawn Guo * 1) Software should trigger IRQ #32 (IOMUX) to be always pending 3499cdde721SShawn Guo * by setting IOMUX_GPR1_GINT. 3509cdde721SShawn Guo * 2) Software should then unmask IRQ #32 in GPC before setting CCM 3519cdde721SShawn Guo * Low-Power mode. 3529cdde721SShawn Guo * 3) Software should mask IRQ #32 right after CCM Low-Power mode 3539cdde721SShawn Guo * is set (set bits 0-1 of CCM_CLPCR). 354b923ff6aSMarc Zyngier * 355b923ff6aSMarc Zyngier * Note that IRQ #32 is GIC SPI #0. 3569cdde721SShawn Guo */ 357b923ff6aSMarc Zyngier imx_gpc_hwirq_unmask(0); 3589cdde721SShawn Guo writel_relaxed(val, ccm_base + CLPCR); 359b923ff6aSMarc Zyngier imx_gpc_hwirq_mask(0); 3609cdde721SShawn Guo 3619cdde721SShawn Guo return 0; 3629cdde721SShawn Guo } 3639cdde721SShawn Guo 3649cdde721SShawn Guo static int imx6q_suspend_finish(unsigned long val) 3659cdde721SShawn Guo { 3669cdde721SShawn Guo if (!imx6_suspend_in_ocram_fn) { 3679cdde721SShawn Guo cpu_do_idle(); 3689cdde721SShawn Guo } else { 3699cdde721SShawn Guo /* 3709cdde721SShawn Guo * call low level suspend function in ocram, 3719cdde721SShawn Guo * as we need to float DDR IO. 3729cdde721SShawn Guo */ 3739cdde721SShawn Guo local_flush_tlb_all(); 374ee4a5f83SAnson Huang /* check if need to flush internal L2 cache */ 375ee4a5f83SAnson Huang if (!((struct imx6_cpu_pm_info *) 376ee4a5f83SAnson Huang suspend_ocram_base)->l2_base.vbase) 377ee4a5f83SAnson Huang flush_cache_all(); 3789cdde721SShawn Guo imx6_suspend_in_ocram_fn(suspend_ocram_base); 3799cdde721SShawn Guo } 3809cdde721SShawn Guo 3819cdde721SShawn Guo return 0; 3829cdde721SShawn Guo } 3839cdde721SShawn Guo 3849cdde721SShawn Guo static int imx6q_pm_enter(suspend_state_t state) 3859cdde721SShawn Guo { 3869cdde721SShawn Guo switch (state) { 38780c0ecdcSAnson Huang case PM_SUSPEND_STANDBY: 3888fb76a07SShawn Guo imx6_set_lpm(STOP_POWER_ON); 3898765caa5SAnson Huang imx6_set_int_mem_clk_lpm(true); 39080c0ecdcSAnson Huang imx_gpc_pre_suspend(false); 39180c0ecdcSAnson Huang if (cpu_is_imx6sl()) 39280c0ecdcSAnson Huang imx6sl_set_wait_clk(true); 39380c0ecdcSAnson Huang /* Zzz ... */ 39480c0ecdcSAnson Huang cpu_do_idle(); 39580c0ecdcSAnson Huang if (cpu_is_imx6sl()) 39680c0ecdcSAnson Huang imx6sl_set_wait_clk(false); 39780c0ecdcSAnson Huang imx_gpc_post_resume(); 3988fb76a07SShawn Guo imx6_set_lpm(WAIT_CLOCKED); 39980c0ecdcSAnson Huang break; 4009cdde721SShawn Guo case PM_SUSPEND_MEM: 4018fb76a07SShawn Guo imx6_set_lpm(STOP_POWER_OFF); 4028765caa5SAnson Huang imx6_set_int_mem_clk_lpm(false); 4039cdde721SShawn Guo imx6q_enable_wb(true); 4049cdde721SShawn Guo /* 4059cdde721SShawn Guo * For suspend into ocram, asm code already take care of 4069cdde721SShawn Guo * RBC setting, so we do NOT need to do that here. 4079cdde721SShawn Guo */ 4089cdde721SShawn Guo if (!imx6_suspend_in_ocram_fn) 40905136f08SAnson Huang imx6_enable_rbc(true); 41080c0ecdcSAnson Huang imx_gpc_pre_suspend(true); 4119cdde721SShawn Guo imx_anatop_pre_suspend(); 4129cdde721SShawn Guo /* Zzz ... */ 4139cdde721SShawn Guo cpu_suspend(0, imx6q_suspend_finish); 4149cdde721SShawn Guo if (cpu_is_imx6q() || cpu_is_imx6dl()) 4159cdde721SShawn Guo imx_smp_prepare(); 4169cdde721SShawn Guo imx_anatop_post_resume(); 4179cdde721SShawn Guo imx_gpc_post_resume(); 41805136f08SAnson Huang imx6_enable_rbc(false); 4199cdde721SShawn Guo imx6q_enable_wb(false); 4208765caa5SAnson Huang imx6_set_int_mem_clk_lpm(true); 4218fb76a07SShawn Guo imx6_set_lpm(WAIT_CLOCKED); 4229cdde721SShawn Guo break; 4239cdde721SShawn Guo default: 4249cdde721SShawn Guo return -EINVAL; 4259cdde721SShawn Guo } 4269cdde721SShawn Guo 4279cdde721SShawn Guo return 0; 4289cdde721SShawn Guo } 4299cdde721SShawn Guo 43080c0ecdcSAnson Huang static int imx6q_pm_valid(suspend_state_t state) 43180c0ecdcSAnson Huang { 43280c0ecdcSAnson Huang return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); 43380c0ecdcSAnson Huang } 43480c0ecdcSAnson Huang 4359cdde721SShawn Guo static const struct platform_suspend_ops imx6q_pm_ops = { 4369cdde721SShawn Guo .enter = imx6q_pm_enter, 43780c0ecdcSAnson Huang .valid = imx6q_pm_valid, 4389cdde721SShawn Guo }; 4399cdde721SShawn Guo 4409cdde721SShawn Guo static int __init imx6_pm_get_base(struct imx6_pm_base *base, 4419cdde721SShawn Guo const char *compat) 4429cdde721SShawn Guo { 4439cdde721SShawn Guo struct device_node *node; 4449cdde721SShawn Guo struct resource res; 4459cdde721SShawn Guo int ret = 0; 4469cdde721SShawn Guo 4479cdde721SShawn Guo node = of_find_compatible_node(NULL, NULL, compat); 448258172f9SFabio Estevam if (!node) 449258172f9SFabio Estevam return -ENODEV; 4509cdde721SShawn Guo 4519cdde721SShawn Guo ret = of_address_to_resource(node, 0, &res); 4529cdde721SShawn Guo if (ret) 4539cdde721SShawn Guo goto put_node; 4549cdde721SShawn Guo 4559cdde721SShawn Guo base->pbase = res.start; 4569cdde721SShawn Guo base->vbase = ioremap(res.start, resource_size(&res)); 4579cdde721SShawn Guo if (!base->vbase) 4589cdde721SShawn Guo ret = -ENOMEM; 4599cdde721SShawn Guo 4609cdde721SShawn Guo put_node: 4619cdde721SShawn Guo of_node_put(node); 4629cdde721SShawn Guo return ret; 4639cdde721SShawn Guo } 4649cdde721SShawn Guo 4659cdde721SShawn Guo static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) 4669cdde721SShawn Guo { 4679cdde721SShawn Guo phys_addr_t ocram_pbase; 4689cdde721SShawn Guo struct device_node *node; 4699cdde721SShawn Guo struct platform_device *pdev; 4709cdde721SShawn Guo struct imx6_cpu_pm_info *pm_info; 4719cdde721SShawn Guo struct gen_pool *ocram_pool; 4729cdde721SShawn Guo unsigned long ocram_base; 4739cdde721SShawn Guo int i, ret = 0; 4749cdde721SShawn Guo const u32 *mmdc_offset_array; 4759cdde721SShawn Guo 4769cdde721SShawn Guo suspend_set_ops(&imx6q_pm_ops); 4779cdde721SShawn Guo 4789cdde721SShawn Guo if (!socdata) { 4799cdde721SShawn Guo pr_warn("%s: invalid argument!\n", __func__); 4809cdde721SShawn Guo return -EINVAL; 4819cdde721SShawn Guo } 4829cdde721SShawn Guo 4839cdde721SShawn Guo node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 4849cdde721SShawn Guo if (!node) { 4859cdde721SShawn Guo pr_warn("%s: failed to find ocram node!\n", __func__); 4869cdde721SShawn Guo return -ENODEV; 4879cdde721SShawn Guo } 4889cdde721SShawn Guo 4899cdde721SShawn Guo pdev = of_find_device_by_node(node); 4909cdde721SShawn Guo if (!pdev) { 4919cdde721SShawn Guo pr_warn("%s: failed to find ocram device!\n", __func__); 4929cdde721SShawn Guo ret = -ENODEV; 4939cdde721SShawn Guo goto put_node; 4949cdde721SShawn Guo } 4959cdde721SShawn Guo 49673858173SVladimir Zapolskiy ocram_pool = gen_pool_get(&pdev->dev, NULL); 4979cdde721SShawn Guo if (!ocram_pool) { 4989cdde721SShawn Guo pr_warn("%s: ocram pool unavailable!\n", __func__); 4999cdde721SShawn Guo ret = -ENODEV; 5009cdde721SShawn Guo goto put_node; 5019cdde721SShawn Guo } 5029cdde721SShawn Guo 5039cdde721SShawn Guo ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); 5049cdde721SShawn Guo if (!ocram_base) { 5059cdde721SShawn Guo pr_warn("%s: unable to alloc ocram!\n", __func__); 5069cdde721SShawn Guo ret = -ENOMEM; 5079cdde721SShawn Guo goto put_node; 5089cdde721SShawn Guo } 5099cdde721SShawn Guo 5109cdde721SShawn Guo ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); 5119cdde721SShawn Guo 5129cdde721SShawn Guo suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, 5139cdde721SShawn Guo MX6Q_SUSPEND_OCRAM_SIZE, false); 5149cdde721SShawn Guo 515ee4a5f83SAnson Huang memset(suspend_ocram_base, 0, sizeof(*pm_info)); 5169cdde721SShawn Guo pm_info = suspend_ocram_base; 5179cdde721SShawn Guo pm_info->pbase = ocram_pbase; 51864fc2a94SFlorian Fainelli pm_info->resume_addr = __pa_symbol(v7_cpu_resume); 5199cdde721SShawn Guo pm_info->pm_info_size = sizeof(*pm_info); 5209cdde721SShawn Guo 5219cdde721SShawn Guo /* 5229cdde721SShawn Guo * ccm physical address is not used by asm code currently, 523f0b478b5SShawn Guo * so get ccm virtual address directly. 5249cdde721SShawn Guo */ 5259cdde721SShawn Guo pm_info->ccm_base.vbase = ccm_base; 5269cdde721SShawn Guo 5279cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); 5289cdde721SShawn Guo if (ret) { 5299cdde721SShawn Guo pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); 5309cdde721SShawn Guo goto put_node; 5319cdde721SShawn Guo } 5329cdde721SShawn Guo 5339cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); 5349cdde721SShawn Guo if (ret) { 5359cdde721SShawn Guo pr_warn("%s: failed to get src base %d!\n", __func__, ret); 5369cdde721SShawn Guo goto src_map_failed; 5379cdde721SShawn Guo } 5389cdde721SShawn Guo 5399cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); 5409cdde721SShawn Guo if (ret) { 5419cdde721SShawn Guo pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); 5429cdde721SShawn Guo goto iomuxc_map_failed; 5439cdde721SShawn Guo } 5449cdde721SShawn Guo 5459cdde721SShawn Guo ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); 5469cdde721SShawn Guo if (ret) { 5479cdde721SShawn Guo pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); 5489cdde721SShawn Guo goto gpc_map_failed; 5499cdde721SShawn Guo } 5509cdde721SShawn Guo 551ee4a5f83SAnson Huang if (socdata->pl310_compat) { 552ee4a5f83SAnson Huang ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); 5539cdde721SShawn Guo if (ret) { 5549cdde721SShawn Guo pr_warn("%s: failed to get pl310-cache base %d!\n", 5559cdde721SShawn Guo __func__, ret); 5569cdde721SShawn Guo goto pl310_cache_map_failed; 5579cdde721SShawn Guo } 558ee4a5f83SAnson Huang } 5599cdde721SShawn Guo 560ec336b28SAnson Huang pm_info->ddr_type = imx_mmdc_get_ddr_type(); 5619cdde721SShawn Guo pm_info->mmdc_io_num = socdata->mmdc_io_num; 5629cdde721SShawn Guo mmdc_offset_array = socdata->mmdc_io_offset; 5639cdde721SShawn Guo 5649cdde721SShawn Guo for (i = 0; i < pm_info->mmdc_io_num; i++) { 5659cdde721SShawn Guo pm_info->mmdc_io_val[i][0] = 5669cdde721SShawn Guo mmdc_offset_array[i]; 5679cdde721SShawn Guo pm_info->mmdc_io_val[i][1] = 5689cdde721SShawn Guo readl_relaxed(pm_info->iomuxc_base.vbase + 5699cdde721SShawn Guo mmdc_offset_array[i]); 5709cdde721SShawn Guo } 5719cdde721SShawn Guo 5729cdde721SShawn Guo imx6_suspend_in_ocram_fn = fncpy( 5739cdde721SShawn Guo suspend_ocram_base + sizeof(*pm_info), 5749cdde721SShawn Guo &imx6_suspend, 5759cdde721SShawn Guo MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); 5769cdde721SShawn Guo 5779cdde721SShawn Guo goto put_node; 5789cdde721SShawn Guo 5799cdde721SShawn Guo pl310_cache_map_failed: 580cfefb762SJean-Christophe Dubois iounmap(pm_info->gpc_base.vbase); 5819cdde721SShawn Guo gpc_map_failed: 582cfefb762SJean-Christophe Dubois iounmap(pm_info->iomuxc_base.vbase); 5839cdde721SShawn Guo iomuxc_map_failed: 584cfefb762SJean-Christophe Dubois iounmap(pm_info->src_base.vbase); 5859cdde721SShawn Guo src_map_failed: 586cfefb762SJean-Christophe Dubois iounmap(pm_info->mmdc_base.vbase); 5879cdde721SShawn Guo put_node: 5889cdde721SShawn Guo of_node_put(node); 5899cdde721SShawn Guo 5909cdde721SShawn Guo return ret; 5919cdde721SShawn Guo } 5929cdde721SShawn Guo 5939cdde721SShawn Guo static void __init imx6_pm_common_init(const struct imx6_pm_socdata 5949cdde721SShawn Guo *socdata) 5959cdde721SShawn Guo { 5969cdde721SShawn Guo struct regmap *gpr; 5979cdde721SShawn Guo int ret; 5989cdde721SShawn Guo 5999cdde721SShawn Guo WARN_ON(!ccm_base); 6009cdde721SShawn Guo 6019cdde721SShawn Guo if (IS_ENABLED(CONFIG_SUSPEND)) { 6029cdde721SShawn Guo ret = imx6q_suspend_init(socdata); 6039cdde721SShawn Guo if (ret) 6049cdde721SShawn Guo pr_warn("%s: No DDR LPM support with suspend %d!\n", 6059cdde721SShawn Guo __func__, ret); 6069cdde721SShawn Guo } 6079cdde721SShawn Guo 6089cdde721SShawn Guo /* 6099cdde721SShawn Guo * This is for SW workaround step #1 of ERR007265, see comments 6108fb76a07SShawn Guo * in imx6_set_lpm for details of this errata. 6119cdde721SShawn Guo * Force IOMUXC irq pending, so that the interrupt to GPC can be 6129cdde721SShawn Guo * used to deassert dsm_request signal when the signal gets 6139cdde721SShawn Guo * asserted unexpectedly. 6149cdde721SShawn Guo */ 6159cdde721SShawn Guo gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 6169cdde721SShawn Guo if (!IS_ERR(gpr)) 6179cdde721SShawn Guo regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, 6189cdde721SShawn Guo IMX6Q_GPR1_GINT); 6199cdde721SShawn Guo } 6209cdde721SShawn Guo 62135e2916fSShawn Guo void __init imx6_pm_ccm_init(const char *ccm_compat) 62235e2916fSShawn Guo { 62335e2916fSShawn Guo struct device_node *np; 62435e2916fSShawn Guo u32 val; 62535e2916fSShawn Guo 62635e2916fSShawn Guo np = of_find_compatible_node(NULL, NULL, ccm_compat); 62735e2916fSShawn Guo ccm_base = of_iomap(np, 0); 62835e2916fSShawn Guo BUG_ON(!ccm_base); 62935e2916fSShawn Guo 63035e2916fSShawn Guo /* 63135e2916fSShawn Guo * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core 63235e2916fSShawn Guo * clock being shut down unexpectedly by WAIT mode. 63335e2916fSShawn Guo */ 63435e2916fSShawn Guo val = readl_relaxed(ccm_base + CLPCR); 63535e2916fSShawn Guo val &= ~BM_CLPCR_LPM; 63635e2916fSShawn Guo writel_relaxed(val, ccm_base + CLPCR); 63735e2916fSShawn Guo } 63835e2916fSShawn Guo 6399cdde721SShawn Guo void __init imx6q_pm_init(void) 6409cdde721SShawn Guo { 6419cdde721SShawn Guo imx6_pm_common_init(&imx6q_pm_data); 6429cdde721SShawn Guo } 6439cdde721SShawn Guo 6449cdde721SShawn Guo void __init imx6dl_pm_init(void) 6459cdde721SShawn Guo { 6469cdde721SShawn Guo imx6_pm_common_init(&imx6dl_pm_data); 6479cdde721SShawn Guo } 6489cdde721SShawn Guo 6499cdde721SShawn Guo void __init imx6sl_pm_init(void) 6509cdde721SShawn Guo { 651d082852fSAnson Huang struct regmap *gpr; 652d082852fSAnson Huang 653d082852fSAnson Huang if (cpu_is_imx6sl()) { 6549cdde721SShawn Guo imx6_pm_common_init(&imx6sl_pm_data); 655d082852fSAnson Huang } else { 65622021948SAnson Huang imx6_pm_common_init(&imx6sll_pm_data); 657d082852fSAnson Huang gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 658d082852fSAnson Huang if (!IS_ERR(gpr)) 659d082852fSAnson Huang regmap_update_bits(gpr, IOMUXC_GPR5, 660d082852fSAnson Huang IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); 661d082852fSAnson Huang } 6629cdde721SShawn Guo } 663ff843d62SAnson Huang 664ff843d62SAnson Huang void __init imx6sx_pm_init(void) 665ff843d62SAnson Huang { 666ff843d62SAnson Huang imx6_pm_common_init(&imx6sx_pm_data); 667ff843d62SAnson Huang } 668ee4a5f83SAnson Huang 669ee4a5f83SAnson Huang void __init imx6ul_pm_init(void) 670ee4a5f83SAnson Huang { 671ee4a5f83SAnson Huang imx6_pm_common_init(&imx6ul_pm_data); 672ee4a5f83SAnson Huang } 673