1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 #include <linux/suspend.h> 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/err.h> 15 #include <linux/export.h> 16 #include <asm/cacheflush.h> 17 #include <asm/system_misc.h> 18 #include <asm/tlbflush.h> 19 20 #include "common.h" 21 #include "cpuidle.h" 22 #include "crm-regs-imx5.h" 23 #include "hardware.h" 24 25 /* 26 * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. 27 * This is also the lowest power state possible without affecting 28 * non-cpu parts of the system. For these reasons, imx5 should default 29 * to always using this state for cpu idling. The PM_SUSPEND_STANDBY also 30 * uses this state and needs to take no action when registers remain confgiured 31 * for this state. 32 */ 33 #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF 34 35 /* 36 * set cpu low power mode before WFI instruction. This function is called 37 * mx5 because it can be used for mx50, mx51, and mx53. 38 */ 39 static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) 40 { 41 u32 plat_lpc, arm_srpgcr, ccm_clpcr; 42 u32 empgc0, empgc1; 43 int stop_mode = 0; 44 45 /* always allow platform to issue a deep sleep mode request */ 46 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & 47 ~(MXC_CORTEXA8_PLAT_LPC_DSM); 48 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); 49 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); 50 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); 51 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); 52 53 switch (mode) { 54 case WAIT_CLOCKED: 55 break; 56 case WAIT_UNCLOCKED: 57 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; 58 break; 59 case WAIT_UNCLOCKED_POWER_OFF: 60 case STOP_POWER_OFF: 61 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM 62 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; 63 if (mode == WAIT_UNCLOCKED_POWER_OFF) { 64 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; 65 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; 66 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; 67 stop_mode = 0; 68 } else { 69 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; 70 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; 71 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; 72 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; 73 stop_mode = 1; 74 } 75 arm_srpgcr |= MXC_SRPGCR_PCR; 76 break; 77 case STOP_POWER_ON: 78 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; 79 break; 80 default: 81 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); 82 return; 83 } 84 85 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); 86 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); 87 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); 88 89 /* Enable NEON SRPG for all but MX50TO1.0. */ 90 if (mx50_revision() != IMX_CHIP_REVISION_1_0) 91 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); 92 93 if (stop_mode) { 94 empgc0 |= MXC_SRPGCR_PCR; 95 empgc1 |= MXC_SRPGCR_PCR; 96 97 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); 98 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); 99 } 100 } 101 102 static int mx5_suspend_enter(suspend_state_t state) 103 { 104 switch (state) { 105 case PM_SUSPEND_MEM: 106 mx5_cpu_lp_set(STOP_POWER_OFF); 107 break; 108 case PM_SUSPEND_STANDBY: 109 /* DEFAULT_IDLE_STATE already configured */ 110 break; 111 default: 112 return -EINVAL; 113 } 114 115 if (state == PM_SUSPEND_MEM) { 116 local_flush_tlb_all(); 117 flush_cache_all(); 118 119 /*clear the EMPGC0/1 bits */ 120 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); 121 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); 122 } 123 cpu_do_idle(); 124 125 /* return registers to default idle state */ 126 mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); 127 return 0; 128 } 129 130 static int mx5_pm_valid(suspend_state_t state) 131 { 132 return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); 133 } 134 135 static const struct platform_suspend_ops mx5_suspend_ops = { 136 .valid = mx5_pm_valid, 137 .enter = mx5_suspend_enter, 138 }; 139 140 static inline int imx5_cpu_do_idle(void) 141 { 142 int ret = tzic_enable_wake(); 143 144 if (likely(!ret)) 145 cpu_do_idle(); 146 147 return ret; 148 } 149 150 static void imx5_pm_idle(void) 151 { 152 imx5_cpu_do_idle(); 153 } 154 155 static int imx5_cpuidle_enter(struct cpuidle_device *dev, 156 struct cpuidle_driver *drv, int idx) 157 { 158 int ret; 159 160 ret = imx5_cpu_do_idle(); 161 if (ret < 0) 162 return ret; 163 164 return idx; 165 } 166 167 static struct cpuidle_driver imx5_cpuidle_driver = { 168 .name = "imx5_cpuidle", 169 .owner = THIS_MODULE, 170 .en_core_tk_irqen = 1, 171 .states[0] = { 172 .enter = imx5_cpuidle_enter, 173 .exit_latency = 2, 174 .target_residency = 1, 175 .flags = CPUIDLE_FLAG_TIME_VALID, 176 .name = "IMX5 SRPG", 177 .desc = "CPU state retained,powered off", 178 }, 179 .state_count = 1, 180 }; 181 182 static int __init imx5_pm_common_init(void) 183 { 184 int ret; 185 struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); 186 187 if (IS_ERR(gpc_dvfs_clk)) 188 return PTR_ERR(gpc_dvfs_clk); 189 190 ret = clk_prepare_enable(gpc_dvfs_clk); 191 if (ret) 192 return ret; 193 194 arm_pm_idle = imx5_pm_idle; 195 196 /* Set the registers to the default cpu idle state. */ 197 mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); 198 199 imx_cpuidle_init(&imx5_cpuidle_driver); 200 return 0; 201 } 202 203 void __init imx51_pm_init(void) 204 { 205 int ret = imx5_pm_common_init(); 206 if (!ret) 207 suspend_set_ops(&mx5_suspend_ops); 208 } 209 210 void __init imx53_pm_init(void) 211 { 212 imx5_pm_common_init(); 213 } 214