1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 #include <linux/suspend.h> 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/err.h> 15 #include <linux/export.h> 16 #include <asm/cacheflush.h> 17 #include <asm/system_misc.h> 18 #include <asm/tlbflush.h> 19 20 #include "common.h" 21 #include "cpuidle.h" 22 #include "crm-regs-imx5.h" 23 #include "hardware.h" 24 25 /* 26 * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. 27 * This is also the lowest power state possible without affecting 28 * non-cpu parts of the system. For these reasons, imx5 should default 29 * to always using this state for cpu idling. The PM_SUSPEND_STANDBY also 30 * uses this state and needs to take no action when registers remain confgiured 31 * for this state. 32 */ 33 #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF 34 35 /* 36 * set cpu low power mode before WFI instruction. This function is called 37 * mx5 because it can be used for mx51, and mx53. 38 */ 39 static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) 40 { 41 u32 plat_lpc, arm_srpgcr, ccm_clpcr; 42 u32 empgc0, empgc1; 43 int stop_mode = 0; 44 45 /* always allow platform to issue a deep sleep mode request */ 46 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & 47 ~(MXC_CORTEXA8_PLAT_LPC_DSM); 48 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); 49 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); 50 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); 51 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); 52 53 switch (mode) { 54 case WAIT_CLOCKED: 55 break; 56 case WAIT_UNCLOCKED: 57 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; 58 break; 59 case WAIT_UNCLOCKED_POWER_OFF: 60 case STOP_POWER_OFF: 61 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM 62 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; 63 if (mode == WAIT_UNCLOCKED_POWER_OFF) { 64 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; 65 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; 66 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; 67 stop_mode = 0; 68 } else { 69 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; 70 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; 71 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; 72 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; 73 stop_mode = 1; 74 } 75 arm_srpgcr |= MXC_SRPGCR_PCR; 76 break; 77 case STOP_POWER_ON: 78 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; 79 break; 80 default: 81 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); 82 return; 83 } 84 85 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); 86 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); 87 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); 88 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); 89 90 if (stop_mode) { 91 empgc0 |= MXC_SRPGCR_PCR; 92 empgc1 |= MXC_SRPGCR_PCR; 93 94 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); 95 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); 96 } 97 } 98 99 static int mx5_suspend_enter(suspend_state_t state) 100 { 101 switch (state) { 102 case PM_SUSPEND_MEM: 103 mx5_cpu_lp_set(STOP_POWER_OFF); 104 break; 105 case PM_SUSPEND_STANDBY: 106 /* DEFAULT_IDLE_STATE already configured */ 107 break; 108 default: 109 return -EINVAL; 110 } 111 112 if (state == PM_SUSPEND_MEM) { 113 local_flush_tlb_all(); 114 flush_cache_all(); 115 116 /*clear the EMPGC0/1 bits */ 117 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); 118 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); 119 } 120 cpu_do_idle(); 121 122 /* return registers to default idle state */ 123 mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); 124 return 0; 125 } 126 127 static int mx5_pm_valid(suspend_state_t state) 128 { 129 return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); 130 } 131 132 static const struct platform_suspend_ops mx5_suspend_ops = { 133 .valid = mx5_pm_valid, 134 .enter = mx5_suspend_enter, 135 }; 136 137 static inline int imx5_cpu_do_idle(void) 138 { 139 int ret = tzic_enable_wake(); 140 141 if (likely(!ret)) 142 cpu_do_idle(); 143 144 return ret; 145 } 146 147 static void imx5_pm_idle(void) 148 { 149 imx5_cpu_do_idle(); 150 } 151 152 static int __init imx5_pm_common_init(void) 153 { 154 int ret; 155 struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); 156 157 if (IS_ERR(gpc_dvfs_clk)) 158 return PTR_ERR(gpc_dvfs_clk); 159 160 ret = clk_prepare_enable(gpc_dvfs_clk); 161 if (ret) 162 return ret; 163 164 arm_pm_idle = imx5_pm_idle; 165 166 /* Set the registers to the default cpu idle state. */ 167 mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); 168 169 return imx5_cpuidle_init(); 170 } 171 172 void __init imx51_pm_init(void) 173 { 174 int ret = imx5_pm_common_init(); 175 if (!ret) 176 suspend_set_ops(&mx5_suspend_ops); 177 } 178 179 void __init imx53_pm_init(void) 180 { 181 imx5_pm_common_init(); 182 } 183