xref: /openbmc/linux/arch/arm/mach-imx/mxc.h (revision 047f2d94)
1 /*
2  * Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc.
3  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17  * MA 02110-1301, USA.
18  */
19 
20 #ifndef __ASM_ARCH_MXC_H__
21 #define __ASM_ARCH_MXC_H__
22 
23 #include <linux/types.h>
24 
25 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
26 #error "Do not include directly."
27 #endif
28 
29 #define MXC_CPU_MX1		1
30 #define MXC_CPU_MX21		21
31 #define MXC_CPU_MX25		25
32 #define MXC_CPU_MX27		27
33 #define MXC_CPU_MX31		31
34 #define MXC_CPU_MX35		35
35 #define MXC_CPU_MX51		51
36 #define MXC_CPU_MX53		53
37 #define MXC_CPU_IMX6SL		0x60
38 #define MXC_CPU_IMX6DL		0x61
39 #define MXC_CPU_IMX6SX		0x62
40 #define MXC_CPU_IMX6Q		0x63
41 #define MXC_CPU_IMX6UL		0x64
42 #define MXC_CPU_IMX6ULL		0x65
43 /* virtual cpu id for i.mx6ulz */
44 #define MXC_CPU_IMX6ULZ		0x6b
45 #define MXC_CPU_IMX6SLL		0x67
46 #define MXC_CPU_IMX7D		0x72
47 #define MXC_CPU_IMX7ULP		0xff
48 
49 #define IMX_DDR_TYPE_LPDDR2		1
50 
51 #ifndef __ASSEMBLY__
52 extern unsigned int __mxc_cpu_type;
53 
54 #ifdef CONFIG_SOC_IMX6SL
55 static inline bool cpu_is_imx6sl(void)
56 {
57 	return __mxc_cpu_type == MXC_CPU_IMX6SL;
58 }
59 #else
60 static inline bool cpu_is_imx6sl(void)
61 {
62 	return false;
63 }
64 #endif
65 
66 static inline bool cpu_is_imx6dl(void)
67 {
68 	return __mxc_cpu_type == MXC_CPU_IMX6DL;
69 }
70 
71 static inline bool cpu_is_imx6sx(void)
72 {
73 	return __mxc_cpu_type == MXC_CPU_IMX6SX;
74 }
75 
76 static inline bool cpu_is_imx6ul(void)
77 {
78 	return __mxc_cpu_type == MXC_CPU_IMX6UL;
79 }
80 
81 static inline bool cpu_is_imx6ull(void)
82 {
83 	return __mxc_cpu_type == MXC_CPU_IMX6ULL;
84 }
85 
86 static inline bool cpu_is_imx6ulz(void)
87 {
88 	return __mxc_cpu_type == MXC_CPU_IMX6ULZ;
89 }
90 
91 static inline bool cpu_is_imx6sll(void)
92 {
93 	return __mxc_cpu_type == MXC_CPU_IMX6SLL;
94 }
95 
96 static inline bool cpu_is_imx6q(void)
97 {
98 	return __mxc_cpu_type == MXC_CPU_IMX6Q;
99 }
100 
101 static inline bool cpu_is_imx7d(void)
102 {
103 	return __mxc_cpu_type == MXC_CPU_IMX7D;
104 }
105 
106 struct cpu_op {
107 	u32 cpu_rate;
108 };
109 
110 int tzic_enable_wake(void);
111 
112 extern struct cpu_op *(*get_cpu_op)(int *op);
113 #endif
114 
115 #define imx_readl	readl_relaxed
116 #define imx_readw	readw_relaxed
117 #define imx_writel	writel_relaxed
118 #define imx_writew	writew_relaxed
119 
120 #endif /*  __ASM_ARCH_MXC_H__ */
121