150f2de61SShawn Guo /* 250f2de61SShawn Guo * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 350f2de61SShawn Guo */ 450f2de61SShawn Guo 550f2de61SShawn Guo /* 650f2de61SShawn Guo * This program is free software; you can redistribute it and/or modify 750f2de61SShawn Guo * it under the terms of the GNU General Public License version 2 as 850f2de61SShawn Guo * published by the Free Software Foundation. 950f2de61SShawn Guo */ 1050f2de61SShawn Guo 1150f2de61SShawn Guo #ifndef __MACH_MX3x_H__ 1250f2de61SShawn Guo #define __MACH_MX3x_H__ 1350f2de61SShawn Guo 1450f2de61SShawn Guo /* 1550f2de61SShawn Guo * MX31 memory map: 1650f2de61SShawn Guo * 1750f2de61SShawn Guo * Virt Phys Size What 1850f2de61SShawn Guo * --------------------------------------------------------------------------- 1950f2de61SShawn Guo * FC000000 43F00000 1M AIPS 1 2050f2de61SShawn Guo * FC100000 50000000 1M SPBA 2150f2de61SShawn Guo * FC200000 53F00000 1M AIPS 2 2250f2de61SShawn Guo * FC500000 60000000 128M ROMPATCH 2350f2de61SShawn Guo * FC400000 68000000 128M AVIC 2450f2de61SShawn Guo * 70000000 256M IPU (MAX M2) 2550f2de61SShawn Guo * 80000000 256M CSD0 SDRAM/DDR 2650f2de61SShawn Guo * 90000000 256M CSD1 SDRAM/DDR 2750f2de61SShawn Guo * A0000000 128M CS0 Flash 2850f2de61SShawn Guo * A8000000 128M CS1 Flash 2950f2de61SShawn Guo * B0000000 32M CS2 3050f2de61SShawn Guo * B2000000 32M CS3 3150f2de61SShawn Guo * F4000000 B4000000 32M CS4 3250f2de61SShawn Guo * B6000000 32M CS5 3350f2de61SShawn Guo * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers 3450f2de61SShawn Guo * C0000000 64M PCMCIA/CF 3550f2de61SShawn Guo */ 3650f2de61SShawn Guo 3750f2de61SShawn Guo /* 3850f2de61SShawn Guo * L2CC 3950f2de61SShawn Guo */ 4050f2de61SShawn Guo #define MX3x_L2CC_BASE_ADDR 0x30000000 4150f2de61SShawn Guo #define MX3x_L2CC_SIZE SZ_1M 4250f2de61SShawn Guo 4350f2de61SShawn Guo /* 4450f2de61SShawn Guo * AIPS 1 4550f2de61SShawn Guo */ 4650f2de61SShawn Guo #define MX3x_AIPS1_BASE_ADDR 0x43f00000 4750f2de61SShawn Guo #define MX3x_AIPS1_SIZE SZ_1M 4850f2de61SShawn Guo #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 4950f2de61SShawn Guo #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 5050f2de61SShawn Guo #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) 5150f2de61SShawn Guo #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) 5250f2de61SShawn Guo #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) 5350f2de61SShawn Guo #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) 5450f2de61SShawn Guo #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) 5550f2de61SShawn Guo #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) 5650f2de61SShawn Guo #define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) 5750f2de61SShawn Guo #define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) 5850f2de61SShawn Guo #define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) 5950f2de61SShawn Guo #define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) 6050f2de61SShawn Guo #define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) 6150f2de61SShawn Guo #define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) 6250f2de61SShawn Guo #define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) 6350f2de61SShawn Guo #define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) 6450f2de61SShawn Guo #define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) 6550f2de61SShawn Guo #define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) 6650f2de61SShawn Guo 6750f2de61SShawn Guo /* 6850f2de61SShawn Guo * SPBA global module enabled #0 6950f2de61SShawn Guo */ 7050f2de61SShawn Guo #define MX3x_SPBA0_BASE_ADDR 0x50000000 7150f2de61SShawn Guo #define MX3x_SPBA0_SIZE SZ_1M 7250f2de61SShawn Guo #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 7350f2de61SShawn Guo #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 7450f2de61SShawn Guo #define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) 7550f2de61SShawn Guo #define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) 7650f2de61SShawn Guo #define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) 7750f2de61SShawn Guo #define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) 7850f2de61SShawn Guo 7950f2de61SShawn Guo /* 8050f2de61SShawn Guo * AIPS 2 8150f2de61SShawn Guo */ 8250f2de61SShawn Guo #define MX3x_AIPS2_BASE_ADDR 0x53f00000 8350f2de61SShawn Guo #define MX3x_AIPS2_SIZE SZ_1M 8450f2de61SShawn Guo #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 8550f2de61SShawn Guo #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 8650f2de61SShawn Guo #define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) 8750f2de61SShawn Guo #define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) 8850f2de61SShawn Guo #define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) 8950f2de61SShawn Guo #define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) 9050f2de61SShawn Guo #define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) 9150f2de61SShawn Guo #define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) 9250f2de61SShawn Guo #define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) 9350f2de61SShawn Guo #define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) 9450f2de61SShawn Guo #define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) 9550f2de61SShawn Guo #define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) 9650f2de61SShawn Guo #define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) 9750f2de61SShawn Guo #define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) 9850f2de61SShawn Guo #define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) 9950f2de61SShawn Guo #define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) 10050f2de61SShawn Guo 10150f2de61SShawn Guo /* 10250f2de61SShawn Guo * ROMP and AVIC 10350f2de61SShawn Guo */ 10450f2de61SShawn Guo #define MX3x_ROMP_BASE_ADDR 0x60000000 10550f2de61SShawn Guo #define MX3x_ROMP_SIZE SZ_1M 10650f2de61SShawn Guo 10750f2de61SShawn Guo #define MX3x_AVIC_BASE_ADDR 0x68000000 10850f2de61SShawn Guo #define MX3x_AVIC_SIZE SZ_1M 10950f2de61SShawn Guo 11050f2de61SShawn Guo /* 11150f2de61SShawn Guo * Memory regions and CS 11250f2de61SShawn Guo */ 11350f2de61SShawn Guo #define MX3x_IPU_MEM_BASE_ADDR 0x70000000 11450f2de61SShawn Guo #define MX3x_CSD0_BASE_ADDR 0x80000000 11550f2de61SShawn Guo #define MX3x_CSD1_BASE_ADDR 0x90000000 11650f2de61SShawn Guo 11750f2de61SShawn Guo #define MX3x_CS0_BASE_ADDR 0xa0000000 11850f2de61SShawn Guo #define MX3x_CS1_BASE_ADDR 0xa8000000 11950f2de61SShawn Guo #define MX3x_CS2_BASE_ADDR 0xb0000000 12050f2de61SShawn Guo #define MX3x_CS3_BASE_ADDR 0xb2000000 12150f2de61SShawn Guo 12250f2de61SShawn Guo #define MX3x_CS4_BASE_ADDR 0xb4000000 12350f2de61SShawn Guo #define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 12450f2de61SShawn Guo #define MX3x_CS4_SIZE SZ_32M 12550f2de61SShawn Guo 12650f2de61SShawn Guo #define MX3x_CS5_BASE_ADDR 0xb6000000 12750f2de61SShawn Guo #define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 12850f2de61SShawn Guo #define MX3x_CS5_SIZE SZ_32M 12950f2de61SShawn Guo 13050f2de61SShawn Guo /* 13150f2de61SShawn Guo * NAND, SDRAM, WEIM, M3IF, EMI controllers 13250f2de61SShawn Guo */ 13350f2de61SShawn Guo #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 13450f2de61SShawn Guo #define MX3x_X_MEMC_SIZE SZ_64K 13550f2de61SShawn Guo #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 13650f2de61SShawn Guo #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 13750f2de61SShawn Guo #define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) 13850f2de61SShawn Guo #define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) 13950f2de61SShawn Guo #define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR 14050f2de61SShawn Guo 14150f2de61SShawn Guo #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 14250f2de61SShawn Guo 14350f2de61SShawn Guo /* 14450f2de61SShawn Guo * Interrupt numbers 14550f2de61SShawn Guo */ 14650f2de61SShawn Guo #include <asm/irq.h> 14750f2de61SShawn Guo #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) 14850f2de61SShawn Guo #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) 14950f2de61SShawn Guo #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) 15050f2de61SShawn Guo #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) 15150f2de61SShawn Guo #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) 15250f2de61SShawn Guo #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) 15350f2de61SShawn Guo #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) 15450f2de61SShawn Guo #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) 15550f2de61SShawn Guo #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) 15650f2de61SShawn Guo #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) 15750f2de61SShawn Guo #define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) 15850f2de61SShawn Guo #define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) 15950f2de61SShawn Guo #define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) 16050f2de61SShawn Guo #define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) 16150f2de61SShawn Guo #define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) 16250f2de61SShawn Guo #define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) 16350f2de61SShawn Guo #define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) 16450f2de61SShawn Guo #define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) 16550f2de61SShawn Guo #define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) 16650f2de61SShawn Guo #define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) 16750f2de61SShawn Guo #define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) 16850f2de61SShawn Guo #define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) 16950f2de61SShawn Guo #define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) 17050f2de61SShawn Guo #define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) 17150f2de61SShawn Guo #define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) 17250f2de61SShawn Guo #define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) 17350f2de61SShawn Guo #define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) 17450f2de61SShawn Guo #define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) 17550f2de61SShawn Guo #define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) 17650f2de61SShawn Guo #define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) 17750f2de61SShawn Guo #define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) 17850f2de61SShawn Guo #define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) 17950f2de61SShawn Guo #define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) 18050f2de61SShawn Guo #define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) 18150f2de61SShawn Guo #define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) 18250f2de61SShawn Guo #define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) 18350f2de61SShawn Guo #define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) 18450f2de61SShawn Guo #define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) 18550f2de61SShawn Guo 18650f2de61SShawn Guo #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 18750f2de61SShawn Guo 18850f2de61SShawn Guo /* Mandatory defines used globally */ 18950f2de61SShawn Guo 19050f2de61SShawn Guo #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 19150f2de61SShawn Guo extern int mx35_revision(void); 19250f2de61SShawn Guo extern int mx31_revision(void); 19350f2de61SShawn Guo #endif 19450f2de61SShawn Guo 19550f2de61SShawn Guo #endif /* ifndef __MACH_MX3x_H__ */ 196