1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 * 6 * This contains i.MX27-specific hardware definitions. For those 7 * hardware pieces that are common between i.MX21 and i.MX27, have a 8 * look at mx2x.h. 9 */ 10 11 #ifndef __MACH_MX27_H__ 12 #define __MACH_MX27_H__ 13 14 #define MX27_AIPI_BASE_ADDR 0x10000000 15 #define MX27_AIPI_SIZE SZ_1M 16 #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) 17 #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) 18 #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) 19 #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) 20 #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) 21 #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) 22 #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) 23 #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) 24 #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) 25 #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) 26 #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) 27 #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) 28 #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) 29 #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) 30 #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) 31 #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) 32 #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) 33 #define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) 34 #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 35 #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 36 #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 37 #define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) 38 #define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) 39 #define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) 40 #define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) 41 #define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) 42 #define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) 43 #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) 44 #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) 45 #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) 46 #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) 47 #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) 48 #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) 49 #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) 50 #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) 51 #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) 52 #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) 53 #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) 54 #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) 55 #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) 56 #define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) 57 #define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) 58 #define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) 59 #define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) 60 #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) 61 #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) 62 #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) 63 #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) 64 #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) 65 #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) 66 #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) 67 #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) 68 #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) 69 #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) 70 #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) 71 #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) 72 #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) 73 74 #define MX27_AVIC_BASE_ADDR 0x10040000 75 76 /* ROM patch */ 77 #define MX27_ROMP_BASE_ADDR 0x10041000 78 79 #define MX27_SAHB1_BASE_ADDR 0x80000000 80 #define MX27_SAHB1_SIZE SZ_1M 81 #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) 82 #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) 83 84 /* Memory regions and CS */ 85 #define MX27_SDRAM_BASE_ADDR 0xa0000000 86 #define MX27_CSD1_BASE_ADDR 0xb0000000 87 88 #define MX27_CS0_BASE_ADDR 0xc0000000 89 #define MX27_CS1_BASE_ADDR 0xc8000000 90 #define MX27_CS2_BASE_ADDR 0xd0000000 91 #define MX27_CS3_BASE_ADDR 0xd2000000 92 #define MX27_CS4_BASE_ADDR 0xd4000000 93 #define MX27_CS5_BASE_ADDR 0xd6000000 94 95 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 96 #define MX27_X_MEMC_BASE_ADDR 0xd8000000 97 #define MX27_X_MEMC_SIZE SZ_1M 98 #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) 99 #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) 100 #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) 101 #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) 102 #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) 103 104 #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) 105 #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) 106 #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) 107 #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) 108 109 #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 110 111 /* IRAM */ 112 #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 113 114 #define MX27_IO_P2V(x) IMX_IO_P2V(x) 115 #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) 116 117 /* fixed interrupt numbers */ 118 #include <asm/irq.h> 119 #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) 120 #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) 121 #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) 122 #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) 123 #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) 124 #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) 125 #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7) 126 #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) 127 #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) 128 #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) 129 #define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) 130 #define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) 131 #define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) 132 #define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) 133 #define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) 134 #define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) 135 #define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) 136 #define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) 137 #define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) 138 #define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) 139 #define MX27_INT_KPP (NR_IRQS_LEGACY + 21) 140 #define MX27_INT_RTC (NR_IRQS_LEGACY + 22) 141 #define MX27_INT_PWM (NR_IRQS_LEGACY + 23) 142 #define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) 143 #define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) 144 #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) 145 #define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) 146 #define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) 147 #define MX27_INT_NFC (NR_IRQS_LEGACY + 29) 148 #define MX27_INT_ATA (NR_IRQS_LEGACY + 30) 149 #define MX27_INT_CSI (NR_IRQS_LEGACY + 31) 150 #define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) 151 #define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) 152 #define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) 153 #define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) 154 #define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) 155 #define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) 156 #define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) 157 #define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) 158 #define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) 159 #define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) 160 #define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) 161 #define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) 162 #define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) 163 #define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) 164 #define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) 165 #define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) 166 #define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) 167 #define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) 168 #define MX27_INT_FEC (NR_IRQS_LEGACY + 50) 169 #define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) 170 #define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) 171 #define MX27_INT_VPU (NR_IRQS_LEGACY + 53) 172 #define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) 173 #define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) 174 #define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) 175 #define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) 176 #define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) 177 #define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) 178 #define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) 179 #define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) 180 #define MX27_INT_IIM (NR_IRQS_LEGACY + 62) 181 #define MX27_INT_CCM (NR_IRQS_LEGACY + 63) 182 183 /* fixed DMA request numbers */ 184 #define MX27_DMA_REQ_CSPI3_RX 1 185 #define MX27_DMA_REQ_CSPI3_TX 2 186 #define MX27_DMA_REQ_EXT 3 187 #define MX27_DMA_REQ_MSHC 4 188 #define MX27_DMA_REQ_SDHC2 6 189 #define MX27_DMA_REQ_SDHC1 7 190 #define MX27_DMA_REQ_SSI2_RX0 8 191 #define MX27_DMA_REQ_SSI2_TX0 9 192 #define MX27_DMA_REQ_SSI2_RX1 10 193 #define MX27_DMA_REQ_SSI2_TX1 11 194 #define MX27_DMA_REQ_SSI1_RX0 12 195 #define MX27_DMA_REQ_SSI1_TX0 13 196 #define MX27_DMA_REQ_SSI1_RX1 14 197 #define MX27_DMA_REQ_SSI1_TX1 15 198 #define MX27_DMA_REQ_CSPI2_RX 16 199 #define MX27_DMA_REQ_CSPI2_TX 17 200 #define MX27_DMA_REQ_CSPI1_RX 18 201 #define MX27_DMA_REQ_CSPI1_TX 19 202 #define MX27_DMA_REQ_UART4_RX 20 203 #define MX27_DMA_REQ_UART4_TX 21 204 #define MX27_DMA_REQ_UART3_RX 22 205 #define MX27_DMA_REQ_UART3_TX 23 206 #define MX27_DMA_REQ_UART2_RX 24 207 #define MX27_DMA_REQ_UART2_TX 25 208 #define MX27_DMA_REQ_UART1_RX 26 209 #define MX27_DMA_REQ_UART1_TX 27 210 #define MX27_DMA_REQ_ATA_TX 28 211 #define MX27_DMA_REQ_ATA_RCV 29 212 #define MX27_DMA_REQ_CSI_STAT 30 213 #define MX27_DMA_REQ_CSI_RX 31 214 #define MX27_DMA_REQ_UART5_TX 32 215 #define MX27_DMA_REQ_UART5_RX 33 216 #define MX27_DMA_REQ_UART6_TX 34 217 #define MX27_DMA_REQ_UART6_RX 35 218 #define MX27_DMA_REQ_SDHC3 36 219 #define MX27_DMA_REQ_NFC 37 220 221 #endif /* ifndef __MACH_MX27_H__ */ 222