1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1999,2000 Arm Limited 4 * Copyright (C) 2000 Deep Blue Solutions Ltd 5 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 6 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 7 * - add MX31 specific definitions 8 */ 9 10 #include <linux/mm.h> 11 #include <linux/init.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/pinctrl/machine.h> 15 16 #include <asm/pgtable.h> 17 #include <asm/system_misc.h> 18 #include <asm/hardware/cache-l2x0.h> 19 #include <asm/mach/map.h> 20 21 #include "common.h" 22 #include "crmregs-imx3.h" 23 #include "devices/devices-common.h" 24 #include "hardware.h" 25 #include "iomux-v3.h" 26 27 void __iomem *mx3_ccm_base; 28 29 static void imx3_idle(void) 30 { 31 unsigned long reg = 0; 32 33 __asm__ __volatile__( 34 /* disable I and D cache */ 35 "mrc p15, 0, %0, c1, c0, 0\n" 36 "bic %0, %0, #0x00001000\n" 37 "bic %0, %0, #0x00000004\n" 38 "mcr p15, 0, %0, c1, c0, 0\n" 39 /* invalidate I cache */ 40 "mov %0, #0\n" 41 "mcr p15, 0, %0, c7, c5, 0\n" 42 /* clear and invalidate D cache */ 43 "mov %0, #0\n" 44 "mcr p15, 0, %0, c7, c14, 0\n" 45 /* WFI */ 46 "mov %0, #0\n" 47 "mcr p15, 0, %0, c7, c0, 4\n" 48 "nop\n" "nop\n" "nop\n" "nop\n" 49 "nop\n" "nop\n" "nop\n" 50 /* enable I and D cache */ 51 "mrc p15, 0, %0, c1, c0, 0\n" 52 "orr %0, %0, #0x00001000\n" 53 "orr %0, %0, #0x00000004\n" 54 "mcr p15, 0, %0, c1, c0, 0\n" 55 : "=r" (reg)); 56 } 57 58 static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size, 59 unsigned int mtype, void *caller) 60 { 61 if (mtype == MT_DEVICE) { 62 /* 63 * Access all peripherals below 0x80000000 as nonshared device 64 * on mx3, but leave l2cc alone. Otherwise cache corruptions 65 * can occur. 66 */ 67 if (phys_addr < 0x80000000 && 68 !addr_in_module(phys_addr, MX3x_L2CC)) 69 mtype = MT_DEVICE_NONSHARED; 70 } 71 72 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 73 } 74 75 static void __init imx3_init_l2x0(void) 76 { 77 #ifdef CONFIG_CACHE_L2X0 78 void __iomem *l2x0_base; 79 void __iomem *clkctl_base; 80 81 /* 82 * First of all, we must repair broken chip settings. There are some 83 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These 84 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. 85 * Workaraound is to setup the correct register setting prior enabling the 86 * L2 cache. This should not hurt already working CPUs, as they are using the 87 * same value. 88 */ 89 #define L2_MEM_VAL 0x10 90 91 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); 92 if (clkctl_base != NULL) { 93 writel(0x00000515, clkctl_base + L2_MEM_VAL); 94 iounmap(clkctl_base); 95 } else { 96 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 97 } 98 99 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); 100 if (!l2x0_base) { 101 printk(KERN_ERR "remapping L2 cache area failed\n"); 102 return; 103 } 104 105 l2x0_init(l2x0_base, 0x00030024, 0x00000000); 106 #endif 107 } 108 109 #ifdef CONFIG_SOC_IMX31 110 static struct map_desc mx31_io_desc[] __initdata = { 111 imx_map_entry(MX31, X_MEMC, MT_DEVICE), 112 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), 113 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), 114 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), 115 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), 116 }; 117 118 /* 119 * This function initializes the memory map. It is called during the 120 * system startup to create static physical to virtual memory mappings 121 * for the IO modules. 122 */ 123 void __init mx31_map_io(void) 124 { 125 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); 126 } 127 128 static void imx31_idle(void) 129 { 130 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); 131 reg &= ~MXC_CCM_CCMR_LPM_MASK; 132 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); 133 134 imx3_idle(); 135 } 136 137 void __init imx31_init_early(void) 138 { 139 mxc_set_cpu_type(MXC_CPU_MX31); 140 arch_ioremap_caller = imx3_ioremap_caller; 141 arm_pm_idle = imx31_idle; 142 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 143 } 144 145 void __init mx31_init_irq(void) 146 { 147 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 148 } 149 150 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { 151 .per_2_per_addr = 1677, 152 }; 153 154 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { 155 .ap_2_ap_addr = 423, 156 .ap_2_bp_addr = 829, 157 .bp_2_ap_addr = 1029, 158 }; 159 160 static struct sdma_platform_data imx31_sdma_pdata __initdata = { 161 .fw_name = "sdma-imx31-to2.bin", 162 .script_addrs = &imx31_to2_sdma_script, 163 }; 164 165 static const struct resource imx31_audmux_res[] __initconst = { 166 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), 167 }; 168 169 static const struct resource imx31_rnga_res[] __initconst = { 170 DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), 171 }; 172 173 void __init imx31_soc_init(void) 174 { 175 int to_version = mx31_revision() >> 4; 176 177 imx3_init_l2x0(); 178 179 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 180 mxc_device_init(); 181 182 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 183 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); 184 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); 185 186 pinctrl_provide_dummies(); 187 188 if (to_version == 1) { 189 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", 190 strlen(imx31_sdma_pdata.fw_name)); 191 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; 192 } 193 194 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 195 196 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); 197 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); 198 199 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, 200 ARRAY_SIZE(imx31_audmux_res)); 201 platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, 202 ARRAY_SIZE(imx31_rnga_res)); 203 } 204 #endif /* ifdef CONFIG_SOC_IMX31 */ 205 206 #ifdef CONFIG_SOC_IMX35 207 static struct map_desc mx35_io_desc[] __initdata = { 208 imx_map_entry(MX35, X_MEMC, MT_DEVICE), 209 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), 210 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), 211 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), 212 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), 213 }; 214 215 void __init mx35_map_io(void) 216 { 217 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); 218 } 219 220 static void imx35_idle(void) 221 { 222 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); 223 reg &= ~MXC_CCM_CCMR_LPM_MASK; 224 reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; 225 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); 226 227 imx3_idle(); 228 } 229 230 void __init imx35_init_early(void) 231 { 232 mxc_set_cpu_type(MXC_CPU_MX35); 233 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 234 arm_pm_idle = imx35_idle; 235 arch_ioremap_caller = imx3_ioremap_caller; 236 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); 237 } 238 239 void __init mx35_init_irq(void) 240 { 241 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 242 } 243 244 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { 245 .ap_2_ap_addr = 642, 246 .uart_2_mcu_addr = 817, 247 .mcu_2_app_addr = 747, 248 .uartsh_2_mcu_addr = 1183, 249 .per_2_shp_addr = 1033, 250 .mcu_2_shp_addr = 961, 251 .ata_2_mcu_addr = 1333, 252 .mcu_2_ata_addr = 1252, 253 .app_2_mcu_addr = 683, 254 .shp_2_per_addr = 1111, 255 .shp_2_mcu_addr = 892, 256 }; 257 258 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { 259 .ap_2_ap_addr = 729, 260 .uart_2_mcu_addr = 904, 261 .per_2_app_addr = 1597, 262 .mcu_2_app_addr = 834, 263 .uartsh_2_mcu_addr = 1270, 264 .per_2_shp_addr = 1120, 265 .mcu_2_shp_addr = 1048, 266 .ata_2_mcu_addr = 1429, 267 .mcu_2_ata_addr = 1339, 268 .app_2_per_addr = 1531, 269 .app_2_mcu_addr = 770, 270 .shp_2_per_addr = 1198, 271 .shp_2_mcu_addr = 979, 272 }; 273 274 static struct sdma_platform_data imx35_sdma_pdata __initdata = { 275 .fw_name = "sdma-imx35-to2.bin", 276 .script_addrs = &imx35_to2_sdma_script, 277 }; 278 279 static const struct resource imx35_audmux_res[] __initconst = { 280 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), 281 }; 282 283 void __init imx35_soc_init(void) 284 { 285 int to_version = mx35_revision() >> 4; 286 287 imx3_init_l2x0(); 288 289 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 290 mxc_device_init(); 291 292 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 293 mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 294 mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 295 296 pinctrl_provide_dummies(); 297 if (to_version == 1) { 298 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 299 strlen(imx35_sdma_pdata.fw_name)); 300 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; 301 } 302 303 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 304 305 /* Setup AIPS registers */ 306 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); 307 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); 308 309 /* i.mx35 has the i.mx31 type audmux */ 310 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, 311 ARRAY_SIZE(imx35_audmux_res)); 312 } 313 #endif /* ifdef CONFIG_SOC_IMX35 */ 314