1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1999,2000 Arm Limited 4 * Copyright (C) 2000 Deep Blue Solutions Ltd 5 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 6 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. 7 * - add MX31 specific definitions 8 */ 9 10 #include <linux/mm.h> 11 #include <linux/init.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/pinctrl/machine.h> 15 16 #include <asm/system_misc.h> 17 #include <asm/hardware/cache-l2x0.h> 18 #include <asm/mach/map.h> 19 20 #include "common.h" 21 #include "crmregs-imx3.h" 22 #include "devices/devices-common.h" 23 #include "hardware.h" 24 #include "iomux-v3.h" 25 26 void __iomem *mx3_ccm_base; 27 28 static void imx3_idle(void) 29 { 30 unsigned long reg = 0; 31 32 __asm__ __volatile__( 33 /* disable I and D cache */ 34 "mrc p15, 0, %0, c1, c0, 0\n" 35 "bic %0, %0, #0x00001000\n" 36 "bic %0, %0, #0x00000004\n" 37 "mcr p15, 0, %0, c1, c0, 0\n" 38 /* invalidate I cache */ 39 "mov %0, #0\n" 40 "mcr p15, 0, %0, c7, c5, 0\n" 41 /* clear and invalidate D cache */ 42 "mov %0, #0\n" 43 "mcr p15, 0, %0, c7, c14, 0\n" 44 /* WFI */ 45 "mov %0, #0\n" 46 "mcr p15, 0, %0, c7, c0, 4\n" 47 "nop\n" "nop\n" "nop\n" "nop\n" 48 "nop\n" "nop\n" "nop\n" 49 /* enable I and D cache */ 50 "mrc p15, 0, %0, c1, c0, 0\n" 51 "orr %0, %0, #0x00001000\n" 52 "orr %0, %0, #0x00000004\n" 53 "mcr p15, 0, %0, c1, c0, 0\n" 54 : "=r" (reg)); 55 } 56 57 static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size, 58 unsigned int mtype, void *caller) 59 { 60 if (mtype == MT_DEVICE) { 61 /* 62 * Access all peripherals below 0x80000000 as nonshared device 63 * on mx3, but leave l2cc alone. Otherwise cache corruptions 64 * can occur. 65 */ 66 if (phys_addr < 0x80000000 && 67 !addr_in_module(phys_addr, MX3x_L2CC)) 68 mtype = MT_DEVICE_NONSHARED; 69 } 70 71 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 72 } 73 74 static void __init imx3_init_l2x0(void) 75 { 76 #ifdef CONFIG_CACHE_L2X0 77 void __iomem *l2x0_base; 78 void __iomem *clkctl_base; 79 80 /* 81 * First of all, we must repair broken chip settings. There are some 82 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These 83 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. 84 * Workaraound is to setup the correct register setting prior enabling the 85 * L2 cache. This should not hurt already working CPUs, as they are using the 86 * same value. 87 */ 88 #define L2_MEM_VAL 0x10 89 90 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); 91 if (clkctl_base != NULL) { 92 writel(0x00000515, clkctl_base + L2_MEM_VAL); 93 iounmap(clkctl_base); 94 } else { 95 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 96 } 97 98 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); 99 if (!l2x0_base) { 100 printk(KERN_ERR "remapping L2 cache area failed\n"); 101 return; 102 } 103 104 l2x0_init(l2x0_base, 0x00030024, 0x00000000); 105 #endif 106 } 107 108 #ifdef CONFIG_SOC_IMX31 109 static struct map_desc mx31_io_desc[] __initdata = { 110 imx_map_entry(MX31, X_MEMC, MT_DEVICE), 111 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), 112 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), 113 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), 114 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), 115 }; 116 117 /* 118 * This function initializes the memory map. It is called during the 119 * system startup to create static physical to virtual memory mappings 120 * for the IO modules. 121 */ 122 void __init mx31_map_io(void) 123 { 124 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); 125 } 126 127 static void imx31_idle(void) 128 { 129 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); 130 reg &= ~MXC_CCM_CCMR_LPM_MASK; 131 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); 132 133 imx3_idle(); 134 } 135 136 void __init imx31_init_early(void) 137 { 138 mxc_set_cpu_type(MXC_CPU_MX31); 139 arch_ioremap_caller = imx3_ioremap_caller; 140 arm_pm_idle = imx31_idle; 141 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 142 } 143 144 void __init mx31_init_irq(void) 145 { 146 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 147 } 148 149 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { 150 .per_2_per_addr = 1677, 151 }; 152 153 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { 154 .ap_2_ap_addr = 423, 155 .ap_2_bp_addr = 829, 156 .bp_2_ap_addr = 1029, 157 }; 158 159 static struct sdma_platform_data imx31_sdma_pdata __initdata = { 160 .fw_name = "sdma-imx31-to2.bin", 161 .script_addrs = &imx31_to2_sdma_script, 162 }; 163 164 static const struct resource imx31_audmux_res[] __initconst = { 165 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), 166 }; 167 168 static const struct resource imx31_rnga_res[] __initconst = { 169 DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), 170 }; 171 172 void __init imx31_soc_init(void) 173 { 174 int to_version = mx31_revision() >> 4; 175 176 imx3_init_l2x0(); 177 178 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 179 mxc_device_init(); 180 181 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 182 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); 183 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); 184 185 pinctrl_provide_dummies(); 186 187 if (to_version == 1) { 188 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", 189 strlen(imx31_sdma_pdata.fw_name)); 190 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; 191 } 192 193 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 194 195 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); 196 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); 197 198 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, 199 ARRAY_SIZE(imx31_audmux_res)); 200 platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, 201 ARRAY_SIZE(imx31_rnga_res)); 202 } 203 #endif /* ifdef CONFIG_SOC_IMX31 */ 204 205 #ifdef CONFIG_SOC_IMX35 206 static struct map_desc mx35_io_desc[] __initdata = { 207 imx_map_entry(MX35, X_MEMC, MT_DEVICE), 208 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), 209 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), 210 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), 211 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), 212 }; 213 214 void __init mx35_map_io(void) 215 { 216 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); 217 } 218 219 static void imx35_idle(void) 220 { 221 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); 222 reg &= ~MXC_CCM_CCMR_LPM_MASK; 223 reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; 224 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); 225 226 imx3_idle(); 227 } 228 229 void __init imx35_init_early(void) 230 { 231 mxc_set_cpu_type(MXC_CPU_MX35); 232 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 233 arm_pm_idle = imx35_idle; 234 arch_ioremap_caller = imx3_ioremap_caller; 235 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); 236 } 237 238 void __init mx35_init_irq(void) 239 { 240 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 241 } 242 243 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { 244 .ap_2_ap_addr = 642, 245 .uart_2_mcu_addr = 817, 246 .mcu_2_app_addr = 747, 247 .uartsh_2_mcu_addr = 1183, 248 .per_2_shp_addr = 1033, 249 .mcu_2_shp_addr = 961, 250 .ata_2_mcu_addr = 1333, 251 .mcu_2_ata_addr = 1252, 252 .app_2_mcu_addr = 683, 253 .shp_2_per_addr = 1111, 254 .shp_2_mcu_addr = 892, 255 }; 256 257 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { 258 .ap_2_ap_addr = 729, 259 .uart_2_mcu_addr = 904, 260 .per_2_app_addr = 1597, 261 .mcu_2_app_addr = 834, 262 .uartsh_2_mcu_addr = 1270, 263 .per_2_shp_addr = 1120, 264 .mcu_2_shp_addr = 1048, 265 .ata_2_mcu_addr = 1429, 266 .mcu_2_ata_addr = 1339, 267 .app_2_per_addr = 1531, 268 .app_2_mcu_addr = 770, 269 .shp_2_per_addr = 1198, 270 .shp_2_mcu_addr = 979, 271 }; 272 273 static struct sdma_platform_data imx35_sdma_pdata __initdata = { 274 .fw_name = "sdma-imx35-to2.bin", 275 .script_addrs = &imx35_to2_sdma_script, 276 }; 277 278 static const struct resource imx35_audmux_res[] __initconst = { 279 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), 280 }; 281 282 void __init imx35_soc_init(void) 283 { 284 int to_version = mx35_revision() >> 4; 285 286 imx3_init_l2x0(); 287 288 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 289 mxc_device_init(); 290 291 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 292 mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 293 mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 294 295 pinctrl_provide_dummies(); 296 if (to_version == 1) { 297 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 298 strlen(imx35_sdma_pdata.fw_name)); 299 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; 300 } 301 302 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 303 304 /* Setup AIPS registers */ 305 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); 306 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); 307 308 /* i.mx35 has the i.mx31 type audmux */ 309 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, 310 ARRAY_SIZE(imx35_audmux_res)); 311 } 312 #endif /* ifdef CONFIG_SOC_IMX35 */ 313