1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/clocksource.h> 16 #include <linux/cpu.h> 17 #include <linux/delay.h> 18 #include <linux/export.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_platform.h> 27 #include <linux/opp.h> 28 #include <linux/phy.h> 29 #include <linux/regmap.h> 30 #include <linux/micrel_phy.h> 31 #include <linux/mfd/syscon.h> 32 #include <asm/hardware/cache-l2x0.h> 33 #include <asm/mach/arch.h> 34 #include <asm/mach/map.h> 35 #include <asm/system_misc.h> 36 37 #include "common.h" 38 #include "cpuidle.h" 39 #include "hardware.h" 40 41 static u32 chip_revision; 42 43 int imx6q_revision(void) 44 { 45 return chip_revision; 46 } 47 48 static void __init imx6q_init_revision(void) 49 { 50 u32 rev = imx_anatop_get_digprog(); 51 52 switch (rev & 0xff) { 53 case 0: 54 chip_revision = IMX_CHIP_REVISION_1_0; 55 break; 56 case 1: 57 chip_revision = IMX_CHIP_REVISION_1_1; 58 break; 59 case 2: 60 chip_revision = IMX_CHIP_REVISION_1_2; 61 break; 62 default: 63 chip_revision = IMX_CHIP_REVISION_UNKNOWN; 64 } 65 66 mxc_set_cpu_type(rev >> 16 & 0xff); 67 } 68 69 static void imx6q_restart(char mode, const char *cmd) 70 { 71 struct device_node *np; 72 void __iomem *wdog_base; 73 74 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); 75 wdog_base = of_iomap(np, 0); 76 if (!wdog_base) 77 goto soft; 78 79 imx_src_prepare_restart(); 80 81 /* enable wdog */ 82 writew_relaxed(1 << 2, wdog_base); 83 /* write twice to ensure the request will not get ignored */ 84 writew_relaxed(1 << 2, wdog_base); 85 86 /* wait for reset to assert ... */ 87 mdelay(500); 88 89 pr_err("Watchdog reset failed to assert reset\n"); 90 91 /* delay to allow the serial port to show the message */ 92 mdelay(50); 93 94 soft: 95 /* we'll take a jump through zero as a poor second */ 96 soft_restart(0); 97 } 98 99 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ 100 static int ksz9021rn_phy_fixup(struct phy_device *phydev) 101 { 102 if (IS_BUILTIN(CONFIG_PHYLIB)) { 103 /* min rx data delay */ 104 phy_write(phydev, 0x0b, 0x8105); 105 phy_write(phydev, 0x0c, 0x0000); 106 107 /* max rx/tx clock delay, min rx/tx control delay */ 108 phy_write(phydev, 0x0b, 0x8104); 109 phy_write(phydev, 0x0c, 0xf0f0); 110 phy_write(phydev, 0x0b, 0x104); 111 } 112 113 return 0; 114 } 115 116 static void __init imx6q_sabrelite_cko1_setup(void) 117 { 118 struct clk *cko1_sel, *ahb, *cko1; 119 unsigned long rate; 120 121 cko1_sel = clk_get_sys(NULL, "cko1_sel"); 122 ahb = clk_get_sys(NULL, "ahb"); 123 cko1 = clk_get_sys(NULL, "cko1"); 124 if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) { 125 pr_err("cko1 setup failed!\n"); 126 goto put_clk; 127 } 128 clk_set_parent(cko1_sel, ahb); 129 rate = clk_round_rate(cko1, 16000000); 130 clk_set_rate(cko1, rate); 131 put_clk: 132 if (!IS_ERR(cko1_sel)) 133 clk_put(cko1_sel); 134 if (!IS_ERR(ahb)) 135 clk_put(ahb); 136 if (!IS_ERR(cko1)) 137 clk_put(cko1); 138 } 139 140 static void __init imx6q_sabrelite_init(void) 141 { 142 if (IS_BUILTIN(CONFIG_PHYLIB)) 143 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 144 ksz9021rn_phy_fixup); 145 imx6q_sabrelite_cko1_setup(); 146 } 147 148 static void __init imx6q_1588_init(void) 149 { 150 struct regmap *gpr; 151 152 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 153 if (!IS_ERR(gpr)) 154 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); 155 else 156 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); 157 158 } 159 static void __init imx6q_usb_init(void) 160 { 161 imx_anatop_usb_chrg_detect_disable(); 162 } 163 164 static void __init imx6q_init_machine(void) 165 { 166 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 167 imx6q_sabrelite_init(); 168 169 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 170 171 imx_anatop_init(); 172 imx6q_pm_init(); 173 imx6q_usb_init(); 174 imx6q_1588_init(); 175 } 176 177 #define OCOTP_CFG3 0x440 178 #define OCOTP_CFG3_SPEED_SHIFT 16 179 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 180 181 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) 182 { 183 struct device_node *np; 184 void __iomem *base; 185 u32 val; 186 187 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 188 if (!np) { 189 pr_warn("failed to find ocotp node\n"); 190 return; 191 } 192 193 base = of_iomap(np, 0); 194 if (!base) { 195 pr_warn("failed to map ocotp\n"); 196 goto put_node; 197 } 198 199 val = readl_relaxed(base + OCOTP_CFG3); 200 val >>= OCOTP_CFG3_SPEED_SHIFT; 201 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) 202 if (opp_disable(cpu_dev, 1200000000)) 203 pr_warn("failed to disable 1.2 GHz OPP\n"); 204 205 put_node: 206 of_node_put(np); 207 } 208 209 static void __init imx6q_opp_init(struct device *cpu_dev) 210 { 211 struct device_node *np; 212 213 np = of_find_node_by_path("/cpus/cpu@0"); 214 if (!np) { 215 pr_warn("failed to find cpu0 node\n"); 216 return; 217 } 218 219 cpu_dev->of_node = np; 220 if (of_init_opp_table(cpu_dev)) { 221 pr_warn("failed to init OPP table\n"); 222 goto put_node; 223 } 224 225 imx6q_opp_check_1p2ghz(cpu_dev); 226 227 put_node: 228 of_node_put(np); 229 } 230 231 static struct platform_device imx6q_cpufreq_pdev = { 232 .name = "imx6q-cpufreq", 233 }; 234 235 static void __init imx6q_init_late(void) 236 { 237 /* 238 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point 239 * to run cpuidle on them. 240 */ 241 if (imx6q_revision() > IMX_CHIP_REVISION_1_1) 242 imx6q_cpuidle_init(); 243 244 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { 245 imx6q_opp_init(&imx6q_cpufreq_pdev.dev); 246 platform_device_register(&imx6q_cpufreq_pdev); 247 } 248 } 249 250 static void __init imx6q_map_io(void) 251 { 252 debug_ll_io_init(); 253 imx_scu_map_io(); 254 } 255 256 static void __init imx6q_init_irq(void) 257 { 258 imx6q_init_revision(); 259 l2x0_of_init(0, ~0UL); 260 imx_src_init(); 261 imx_gpc_init(); 262 irqchip_init(); 263 } 264 265 static void __init imx6q_timer_init(void) 266 { 267 mx6q_clocks_init(); 268 clocksource_of_init(); 269 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", 270 imx6q_revision()); 271 } 272 273 static const char *imx6q_dt_compat[] __initdata = { 274 "fsl,imx6dl", 275 "fsl,imx6q", 276 NULL, 277 }; 278 279 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") 280 .smp = smp_ops(imx_smp_ops), 281 .map_io = imx6q_map_io, 282 .init_irq = imx6q_init_irq, 283 .init_time = imx6q_timer_init, 284 .init_machine = imx6q_init_machine, 285 .init_late = imx6q_init_late, 286 .dt_compat = imx6q_dt_compat, 287 .restart = imx6q_restart, 288 MACHINE_END 289