1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/cpu.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_platform.h> 26 #include <linux/opp.h> 27 #include <linux/phy.h> 28 #include <linux/reboot.h> 29 #include <linux/regmap.h> 30 #include <linux/micrel_phy.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 33 #include <asm/mach/arch.h> 34 #include <asm/mach/map.h> 35 #include <asm/system_misc.h> 36 37 #include "common.h" 38 #include "cpuidle.h" 39 #include "hardware.h" 40 41 static u32 chip_revision; 42 43 int imx6q_revision(void) 44 { 45 return chip_revision; 46 } 47 48 static void __init imx6q_init_revision(void) 49 { 50 u32 rev = imx_anatop_get_digprog(); 51 52 switch (rev & 0xff) { 53 case 0: 54 chip_revision = IMX_CHIP_REVISION_1_0; 55 break; 56 case 1: 57 chip_revision = IMX_CHIP_REVISION_1_1; 58 break; 59 case 2: 60 chip_revision = IMX_CHIP_REVISION_1_2; 61 break; 62 default: 63 chip_revision = IMX_CHIP_REVISION_UNKNOWN; 64 } 65 66 mxc_set_cpu_type(rev >> 16 & 0xff); 67 } 68 69 static void imx6q_restart(enum reboot_mode mode, const char *cmd) 70 { 71 struct device_node *np; 72 void __iomem *wdog_base; 73 74 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); 75 wdog_base = of_iomap(np, 0); 76 if (!wdog_base) 77 goto soft; 78 79 imx_src_prepare_restart(); 80 81 /* enable wdog */ 82 writew_relaxed(1 << 2, wdog_base); 83 /* write twice to ensure the request will not get ignored */ 84 writew_relaxed(1 << 2, wdog_base); 85 86 /* wait for reset to assert ... */ 87 mdelay(500); 88 89 pr_err("Watchdog reset failed to assert reset\n"); 90 91 /* delay to allow the serial port to show the message */ 92 mdelay(50); 93 94 soft: 95 /* we'll take a jump through zero as a poor second */ 96 soft_restart(0); 97 } 98 99 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ 100 static int ksz9021rn_phy_fixup(struct phy_device *phydev) 101 { 102 if (IS_BUILTIN(CONFIG_PHYLIB)) { 103 /* min rx data delay */ 104 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 105 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); 106 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); 107 108 /* max rx/tx clock delay, min rx/tx control delay */ 109 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 110 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); 111 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); 112 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 113 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); 114 } 115 116 return 0; 117 } 118 119 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) 120 { 121 phy_write(dev, 0x0d, device); 122 phy_write(dev, 0x0e, reg); 123 phy_write(dev, 0x0d, (1 << 14) | device); 124 phy_write(dev, 0x0e, val); 125 } 126 127 static int ksz9031rn_phy_fixup(struct phy_device *dev) 128 { 129 /* 130 * min rx data delay, max rx/tx clock delay, 131 * min rx/tx control delay 132 */ 133 mmd_write_reg(dev, 2, 4, 0); 134 mmd_write_reg(dev, 2, 5, 0); 135 mmd_write_reg(dev, 2, 8, 0x003ff); 136 137 return 0; 138 } 139 140 static int ar8031_phy_fixup(struct phy_device *dev) 141 { 142 u16 val; 143 144 /* To enable AR8031 output a 125MHz clk from CLK_25M */ 145 phy_write(dev, 0xd, 0x7); 146 phy_write(dev, 0xe, 0x8016); 147 phy_write(dev, 0xd, 0x4007); 148 149 val = phy_read(dev, 0xe); 150 val &= 0xffe3; 151 val |= 0x18; 152 phy_write(dev, 0xe, val); 153 154 /* introduce tx clock delay */ 155 phy_write(dev, 0x1d, 0x5); 156 val = phy_read(dev, 0x1e); 157 val |= 0x0100; 158 phy_write(dev, 0x1e, val); 159 160 return 0; 161 } 162 163 #define PHY_ID_AR8031 0x004dd074 164 165 static void __init imx6q_enet_phy_init(void) 166 { 167 if (IS_BUILTIN(CONFIG_PHYLIB)) { 168 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 169 ksz9021rn_phy_fixup); 170 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, 171 ksz9031rn_phy_fixup); 172 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, 173 ar8031_phy_fixup); 174 } 175 } 176 177 static void __init imx6q_1588_init(void) 178 { 179 struct regmap *gpr; 180 181 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 182 if (!IS_ERR(gpr)) 183 regmap_update_bits(gpr, IOMUXC_GPR1, 184 IMX6Q_GPR1_ENET_CLK_SEL_MASK, 185 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); 186 else 187 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); 188 189 } 190 191 static void __init imx6q_init_machine(void) 192 { 193 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", 194 imx6q_revision()); 195 196 imx6q_enet_phy_init(); 197 198 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 199 200 imx_anatop_init(); 201 imx6q_pm_init(); 202 imx6q_1588_init(); 203 } 204 205 #define OCOTP_CFG3 0x440 206 #define OCOTP_CFG3_SPEED_SHIFT 16 207 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 208 209 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) 210 { 211 struct device_node *np; 212 void __iomem *base; 213 u32 val; 214 215 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 216 if (!np) { 217 pr_warn("failed to find ocotp node\n"); 218 return; 219 } 220 221 base = of_iomap(np, 0); 222 if (!base) { 223 pr_warn("failed to map ocotp\n"); 224 goto put_node; 225 } 226 227 val = readl_relaxed(base + OCOTP_CFG3); 228 val >>= OCOTP_CFG3_SPEED_SHIFT; 229 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) 230 if (opp_disable(cpu_dev, 1200000000)) 231 pr_warn("failed to disable 1.2 GHz OPP\n"); 232 233 put_node: 234 of_node_put(np); 235 } 236 237 static void __init imx6q_opp_init(void) 238 { 239 struct device_node *np; 240 struct device *cpu_dev = get_cpu_device(0); 241 242 if (!cpu_dev) { 243 pr_warn("failed to get cpu0 device\n"); 244 return; 245 } 246 np = of_node_get(cpu_dev->of_node); 247 if (!np) { 248 pr_warn("failed to find cpu0 node\n"); 249 return; 250 } 251 252 if (of_init_opp_table(cpu_dev)) { 253 pr_warn("failed to init OPP table\n"); 254 goto put_node; 255 } 256 257 imx6q_opp_check_1p2ghz(cpu_dev); 258 259 put_node: 260 of_node_put(np); 261 } 262 263 static struct platform_device imx6q_cpufreq_pdev = { 264 .name = "imx6q-cpufreq", 265 }; 266 267 static void __init imx6q_init_late(void) 268 { 269 /* 270 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point 271 * to run cpuidle on them. 272 */ 273 if (imx6q_revision() > IMX_CHIP_REVISION_1_1) 274 imx6q_cpuidle_init(); 275 276 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { 277 imx6q_opp_init(); 278 platform_device_register(&imx6q_cpufreq_pdev); 279 } 280 } 281 282 static void __init imx6q_map_io(void) 283 { 284 debug_ll_io_init(); 285 imx_scu_map_io(); 286 } 287 288 static void __init imx6q_init_irq(void) 289 { 290 imx6q_init_revision(); 291 imx_init_l2cache(); 292 imx_src_init(); 293 imx_gpc_init(); 294 irqchip_init(); 295 } 296 297 static const char *imx6q_dt_compat[] __initdata = { 298 "fsl,imx6dl", 299 "fsl,imx6q", 300 NULL, 301 }; 302 303 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") 304 .smp = smp_ops(imx_smp_ops), 305 .map_io = imx6q_map_io, 306 .init_irq = imx6q_init_irq, 307 .init_machine = imx6q_init_machine, 308 .init_late = imx6q_init_late, 309 .dt_compat = imx6q_dt_compat, 310 .restart = imx6q_restart, 311 MACHINE_END 312