1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clkdev.h> 16 #include <linux/clocksource.h> 17 #include <linux/cpu.h> 18 #include <linux/delay.h> 19 #include <linux/export.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/irqchip.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/opp.h> 29 #include <linux/phy.h> 30 #include <linux/reboot.h> 31 #include <linux/regmap.h> 32 #include <linux/micrel_phy.h> 33 #include <linux/mfd/syscon.h> 34 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 35 #include <asm/mach/arch.h> 36 #include <asm/mach/map.h> 37 #include <asm/system_misc.h> 38 39 #include "common.h" 40 #include "cpuidle.h" 41 #include "hardware.h" 42 43 static u32 chip_revision; 44 45 int imx6q_revision(void) 46 { 47 return chip_revision; 48 } 49 50 static void __init imx6q_init_revision(void) 51 { 52 u32 rev = imx_anatop_get_digprog(); 53 54 switch (rev & 0xff) { 55 case 0: 56 chip_revision = IMX_CHIP_REVISION_1_0; 57 break; 58 case 1: 59 chip_revision = IMX_CHIP_REVISION_1_1; 60 break; 61 case 2: 62 chip_revision = IMX_CHIP_REVISION_1_2; 63 break; 64 default: 65 chip_revision = IMX_CHIP_REVISION_UNKNOWN; 66 } 67 68 mxc_set_cpu_type(rev >> 16 & 0xff); 69 } 70 71 static void imx6q_restart(enum reboot_mode mode, const char *cmd) 72 { 73 struct device_node *np; 74 void __iomem *wdog_base; 75 76 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); 77 wdog_base = of_iomap(np, 0); 78 if (!wdog_base) 79 goto soft; 80 81 imx_src_prepare_restart(); 82 83 /* enable wdog */ 84 writew_relaxed(1 << 2, wdog_base); 85 /* write twice to ensure the request will not get ignored */ 86 writew_relaxed(1 << 2, wdog_base); 87 88 /* wait for reset to assert ... */ 89 mdelay(500); 90 91 pr_err("Watchdog reset failed to assert reset\n"); 92 93 /* delay to allow the serial port to show the message */ 94 mdelay(50); 95 96 soft: 97 /* we'll take a jump through zero as a poor second */ 98 soft_restart(0); 99 } 100 101 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ 102 static int ksz9021rn_phy_fixup(struct phy_device *phydev) 103 { 104 if (IS_BUILTIN(CONFIG_PHYLIB)) { 105 /* min rx data delay */ 106 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 107 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); 108 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); 109 110 /* max rx/tx clock delay, min rx/tx control delay */ 111 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 112 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); 113 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); 114 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 115 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); 116 } 117 118 return 0; 119 } 120 121 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) 122 { 123 phy_write(dev, 0x0d, device); 124 phy_write(dev, 0x0e, reg); 125 phy_write(dev, 0x0d, (1 << 14) | device); 126 phy_write(dev, 0x0e, val); 127 } 128 129 static int ksz9031rn_phy_fixup(struct phy_device *dev) 130 { 131 /* 132 * min rx data delay, max rx/tx clock delay, 133 * min rx/tx control delay 134 */ 135 mmd_write_reg(dev, 2, 4, 0); 136 mmd_write_reg(dev, 2, 5, 0); 137 mmd_write_reg(dev, 2, 8, 0x003ff); 138 139 return 0; 140 } 141 142 static int ar8031_phy_fixup(struct phy_device *dev) 143 { 144 u16 val; 145 146 /* To enable AR8031 output a 125MHz clk from CLK_25M */ 147 phy_write(dev, 0xd, 0x7); 148 phy_write(dev, 0xe, 0x8016); 149 phy_write(dev, 0xd, 0x4007); 150 151 val = phy_read(dev, 0xe); 152 val &= 0xffe3; 153 val |= 0x18; 154 phy_write(dev, 0xe, val); 155 156 /* introduce tx clock delay */ 157 phy_write(dev, 0x1d, 0x5); 158 val = phy_read(dev, 0x1e); 159 val |= 0x0100; 160 phy_write(dev, 0x1e, val); 161 162 return 0; 163 } 164 165 #define PHY_ID_AR8031 0x004dd074 166 167 static void __init imx6q_enet_phy_init(void) 168 { 169 if (IS_BUILTIN(CONFIG_PHYLIB)) { 170 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 171 ksz9021rn_phy_fixup); 172 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, 173 ksz9031rn_phy_fixup); 174 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, 175 ar8031_phy_fixup); 176 } 177 } 178 179 static void __init imx6q_1588_init(void) 180 { 181 struct regmap *gpr; 182 183 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 184 if (!IS_ERR(gpr)) 185 regmap_update_bits(gpr, IOMUXC_GPR1, 186 IMX6Q_GPR1_ENET_CLK_SEL_MASK, 187 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); 188 else 189 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); 190 191 } 192 193 static void __init imx6q_init_machine(void) 194 { 195 imx6q_enet_phy_init(); 196 197 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 198 199 imx_anatop_init(); 200 imx6q_pm_init(); 201 imx6q_1588_init(); 202 } 203 204 #define OCOTP_CFG3 0x440 205 #define OCOTP_CFG3_SPEED_SHIFT 16 206 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 207 208 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) 209 { 210 struct device_node *np; 211 void __iomem *base; 212 u32 val; 213 214 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 215 if (!np) { 216 pr_warn("failed to find ocotp node\n"); 217 return; 218 } 219 220 base = of_iomap(np, 0); 221 if (!base) { 222 pr_warn("failed to map ocotp\n"); 223 goto put_node; 224 } 225 226 val = readl_relaxed(base + OCOTP_CFG3); 227 val >>= OCOTP_CFG3_SPEED_SHIFT; 228 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) 229 if (opp_disable(cpu_dev, 1200000000)) 230 pr_warn("failed to disable 1.2 GHz OPP\n"); 231 232 put_node: 233 of_node_put(np); 234 } 235 236 static void __init imx6q_opp_init(void) 237 { 238 struct device_node *np; 239 struct device *cpu_dev = get_cpu_device(0); 240 241 if (!cpu_dev) { 242 pr_warn("failed to get cpu0 device\n"); 243 return; 244 } 245 np = of_node_get(cpu_dev->of_node); 246 if (!np) { 247 pr_warn("failed to find cpu0 node\n"); 248 return; 249 } 250 251 if (of_init_opp_table(cpu_dev)) { 252 pr_warn("failed to init OPP table\n"); 253 goto put_node; 254 } 255 256 imx6q_opp_check_1p2ghz(cpu_dev); 257 258 put_node: 259 of_node_put(np); 260 } 261 262 static struct platform_device imx6q_cpufreq_pdev = { 263 .name = "imx6q-cpufreq", 264 }; 265 266 static void __init imx6q_init_late(void) 267 { 268 /* 269 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point 270 * to run cpuidle on them. 271 */ 272 if (imx6q_revision() > IMX_CHIP_REVISION_1_1) 273 imx6q_cpuidle_init(); 274 275 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { 276 imx6q_opp_init(); 277 platform_device_register(&imx6q_cpufreq_pdev); 278 } 279 } 280 281 static void __init imx6q_map_io(void) 282 { 283 debug_ll_io_init(); 284 imx_scu_map_io(); 285 } 286 287 static void __init imx6q_init_irq(void) 288 { 289 imx6q_init_revision(); 290 imx_init_l2cache(); 291 imx_src_init(); 292 imx_gpc_init(); 293 irqchip_init(); 294 } 295 296 static void __init imx6q_timer_init(void) 297 { 298 of_clk_init(NULL); 299 clocksource_of_init(); 300 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", 301 imx6q_revision()); 302 } 303 304 static const char *imx6q_dt_compat[] __initdata = { 305 "fsl,imx6dl", 306 "fsl,imx6q", 307 NULL, 308 }; 309 310 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") 311 .smp = smp_ops(imx_smp_ops), 312 .map_io = imx6q_map_io, 313 .init_irq = imx6q_init_irq, 314 .init_time = imx6q_timer_init, 315 .init_machine = imx6q_init_machine, 316 .init_late = imx6q_init_late, 317 .dt_compat = imx6q_dt_compat, 318 .restart = imx6q_restart, 319 MACHINE_END 320