11fc593feSArnd Bergmann/* 21fc593feSArnd Bergmann * Copyright 2011 Freescale Semiconductor, Inc. 31fc593feSArnd Bergmann * Copyright 2011 Linaro Ltd. 41fc593feSArnd Bergmann * 51fc593feSArnd Bergmann * The code contained herein is licensed under the GNU General Public 61fc593feSArnd Bergmann * License. You may obtain a copy of the GNU General Public License 71fc593feSArnd Bergmann * Version 2 or later at the following locations: 81fc593feSArnd Bergmann * 91fc593feSArnd Bergmann * http://www.opensource.org/licenses/gpl-license.html 101fc593feSArnd Bergmann * http://www.gnu.org/copyleft/gpl.html 111fc593feSArnd Bergmann */ 121fc593feSArnd Bergmann 131fc593feSArnd Bergmann#include <linux/linkage.h> 141fc593feSArnd Bergmann#include <linux/init.h> 151fc593feSArnd Bergmann#include <asm/asm-offsets.h> 161fc593feSArnd Bergmann#include <asm/hardware/cache-l2x0.h> 171fc593feSArnd Bergmann 181fc593feSArnd Bergmann .section ".text.head", "ax" 191fc593feSArnd Bergmann 201fc593feSArnd Bergmann#ifdef CONFIG_SMP 21087bb283SShawn Guodiag_reg_offset: 22087bb283SShawn Guo .word g_diag_reg - . 23087bb283SShawn Guo 24087bb283SShawn Guo .macro set_diag_reg 25087bb283SShawn Guo adr r0, diag_reg_offset 26087bb283SShawn Guo ldr r1, [r0] 27087bb283SShawn Guo add r1, r1, r0 @ r1 = physical &g_diag_reg 28087bb283SShawn Guo ldr r0, [r1] 29087bb283SShawn Guo mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 30087bb283SShawn Guo .endm 31087bb283SShawn Guo 321fc593feSArnd BergmannENTRY(v7_secondary_startup) 331fc593feSArnd Bergmann bl v7_invalidate_l1 34087bb283SShawn Guo set_diag_reg 351fc593feSArnd Bergmann b secondary_startup 361fc593feSArnd BergmannENDPROC(v7_secondary_startup) 371fc593feSArnd Bergmann#endif 381fc593feSArnd Bergmann 39cb48389bSArnd Bergmann#ifdef CONFIG_ARM_CPU_SUSPEND 401fc593feSArnd Bergmann/* 41b4e61537SNicolas Pitre * The following code must assume it is running from physical address 42b4e61537SNicolas Pitre * where absolute virtual addresses to the data section have to be 43b4e61537SNicolas Pitre * turned into relative ones. 441fc593feSArnd Bergmann */ 451fc593feSArnd Bergmann 461fc593feSArnd Bergmann#ifdef CONFIG_CACHE_L2X0 471fc593feSArnd Bergmann .macro pl310_resume 48b4e61537SNicolas Pitre adr r0, l2x0_saved_regs_offset 49b4e61537SNicolas Pitre ldr r2, [r0] 50b4e61537SNicolas Pitre add r2, r2, r0 511fc593feSArnd Bergmann ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 521fc593feSArnd Bergmann ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value 531fc593feSArnd Bergmann str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl 541fc593feSArnd Bergmann mov r1, #0x1 551fc593feSArnd Bergmann str r1, [r0, #L2X0_CTRL] @ re-enable L2 561fc593feSArnd Bergmann .endm 571fc593feSArnd Bergmann 58b4e61537SNicolas Pitrel2x0_saved_regs_offset: 59b4e61537SNicolas Pitre .word l2x0_saved_regs - . 60b4e61537SNicolas Pitre 611fc593feSArnd Bergmann#else 621fc593feSArnd Bergmann .macro pl310_resume 631fc593feSArnd Bergmann .endm 641fc593feSArnd Bergmann#endif 651fc593feSArnd Bergmann 661fc593feSArnd BergmannENTRY(v7_cpu_resume) 671fc593feSArnd Bergmann bl v7_invalidate_l1 681fc593feSArnd Bergmann pl310_resume 691fc593feSArnd Bergmann b cpu_resume 701fc593feSArnd BergmannENDPROC(v7_cpu_resume) 711fc593feSArnd Bergmann#endif 72