1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 */ 6 7 #include <linux/io.h> 8 #include <linux/irq.h> 9 #include <linux/irqchip.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 14 #include "common.h" 15 #include "hardware.h" 16 17 #define GPC_CNTR 0x0 18 #define GPC_IMR1 0x008 19 #define GPC_PGC_CPU_PDN 0x2a0 20 #define GPC_PGC_CPU_PUPSCR 0x2a4 21 #define GPC_PGC_CPU_PDNSCR 0x2a8 22 #define GPC_PGC_SW2ISO_SHIFT 0x8 23 #define GPC_PGC_SW_SHIFT 0x0 24 25 #define GPC_CNTR_L2_PGE_SHIFT 22 26 27 #define IMR_NUM 4 28 #define GPC_MAX_IRQS (IMR_NUM * 32) 29 30 static void __iomem *gpc_base; 31 static u32 gpc_wake_irqs[IMR_NUM]; 32 static u32 gpc_saved_imrs[IMR_NUM]; 33 34 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) 35 { 36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 37 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); 38 } 39 40 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw) 41 { 42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 43 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); 44 } 45 46 void imx_gpc_set_arm_power_in_lpm(bool power_off) 47 { 48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); 49 } 50 51 void imx_gpc_set_l2_mem_power_in_lpm(bool power_off) 52 { 53 u32 val; 54 55 val = readl_relaxed(gpc_base + GPC_CNTR); 56 val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); 57 if (power_off) 58 val |= 1 << GPC_CNTR_L2_PGE_SHIFT; 59 writel_relaxed(val, gpc_base + GPC_CNTR); 60 } 61 62 void imx_gpc_pre_suspend(bool arm_power_off) 63 { 64 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 65 int i; 66 67 /* Tell GPC to power off ARM core when suspend */ 68 if (arm_power_off) 69 imx_gpc_set_arm_power_in_lpm(arm_power_off); 70 71 for (i = 0; i < IMR_NUM; i++) { 72 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 73 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); 74 } 75 } 76 77 void imx_gpc_post_resume(void) 78 { 79 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 80 int i; 81 82 /* Keep ARM core powered on for other low-power modes */ 83 imx_gpc_set_arm_power_in_lpm(false); 84 85 for (i = 0; i < IMR_NUM; i++) 86 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 87 } 88 89 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) 90 { 91 unsigned int idx = d->hwirq / 32; 92 u32 mask; 93 94 mask = 1 << d->hwirq % 32; 95 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : 96 gpc_wake_irqs[idx] & ~mask; 97 98 /* 99 * Do *not* call into the parent, as the GIC doesn't have any 100 * wake-up facility... 101 */ 102 return 0; 103 } 104 105 void imx_gpc_mask_all(void) 106 { 107 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 108 int i; 109 110 for (i = 0; i < IMR_NUM; i++) { 111 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 112 writel_relaxed(~0, reg_imr1 + i * 4); 113 } 114 } 115 116 void imx_gpc_restore_all(void) 117 { 118 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 119 int i; 120 121 for (i = 0; i < IMR_NUM; i++) 122 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 123 } 124 125 void imx_gpc_hwirq_unmask(unsigned int hwirq) 126 { 127 void __iomem *reg; 128 u32 val; 129 130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; 131 val = readl_relaxed(reg); 132 val &= ~(1 << hwirq % 32); 133 writel_relaxed(val, reg); 134 } 135 136 void imx_gpc_hwirq_mask(unsigned int hwirq) 137 { 138 void __iomem *reg; 139 u32 val; 140 141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; 142 val = readl_relaxed(reg); 143 val |= 1 << (hwirq % 32); 144 writel_relaxed(val, reg); 145 } 146 147 static void imx_gpc_irq_unmask(struct irq_data *d) 148 { 149 imx_gpc_hwirq_unmask(d->hwirq); 150 irq_chip_unmask_parent(d); 151 } 152 153 static void imx_gpc_irq_mask(struct irq_data *d) 154 { 155 imx_gpc_hwirq_mask(d->hwirq); 156 irq_chip_mask_parent(d); 157 } 158 159 static struct irq_chip imx_gpc_chip = { 160 .name = "GPC", 161 .irq_eoi = irq_chip_eoi_parent, 162 .irq_mask = imx_gpc_irq_mask, 163 .irq_unmask = imx_gpc_irq_unmask, 164 .irq_retrigger = irq_chip_retrigger_hierarchy, 165 .irq_set_wake = imx_gpc_irq_set_wake, 166 .irq_set_type = irq_chip_set_type_parent, 167 #ifdef CONFIG_SMP 168 .irq_set_affinity = irq_chip_set_affinity_parent, 169 #endif 170 }; 171 172 static int imx_gpc_domain_translate(struct irq_domain *d, 173 struct irq_fwspec *fwspec, 174 unsigned long *hwirq, 175 unsigned int *type) 176 { 177 if (is_of_node(fwspec->fwnode)) { 178 if (fwspec->param_count != 3) 179 return -EINVAL; 180 181 /* No PPI should point to this domain */ 182 if (fwspec->param[0] != 0) 183 return -EINVAL; 184 185 *hwirq = fwspec->param[1]; 186 *type = fwspec->param[2]; 187 return 0; 188 } 189 190 return -EINVAL; 191 } 192 193 static int imx_gpc_domain_alloc(struct irq_domain *domain, 194 unsigned int irq, 195 unsigned int nr_irqs, void *data) 196 { 197 struct irq_fwspec *fwspec = data; 198 struct irq_fwspec parent_fwspec; 199 irq_hw_number_t hwirq; 200 int i; 201 202 if (fwspec->param_count != 3) 203 return -EINVAL; /* Not GIC compliant */ 204 if (fwspec->param[0] != 0) 205 return -EINVAL; /* No PPI should point to this domain */ 206 207 hwirq = fwspec->param[1]; 208 if (hwirq >= GPC_MAX_IRQS) 209 return -EINVAL; /* Can't deal with this */ 210 211 for (i = 0; i < nr_irqs; i++) 212 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, 213 &imx_gpc_chip, NULL); 214 215 parent_fwspec = *fwspec; 216 parent_fwspec.fwnode = domain->parent->fwnode; 217 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, 218 &parent_fwspec); 219 } 220 221 static const struct irq_domain_ops imx_gpc_domain_ops = { 222 .translate = imx_gpc_domain_translate, 223 .alloc = imx_gpc_domain_alloc, 224 .free = irq_domain_free_irqs_common, 225 }; 226 227 static int __init imx_gpc_init(struct device_node *node, 228 struct device_node *parent) 229 { 230 struct irq_domain *parent_domain, *domain; 231 int i; 232 233 if (!parent) { 234 pr_err("%pOF: no parent, giving up\n", node); 235 return -ENODEV; 236 } 237 238 parent_domain = irq_find_host(parent); 239 if (!parent_domain) { 240 pr_err("%pOF: unable to obtain parent domain\n", node); 241 return -ENXIO; 242 } 243 244 gpc_base = of_iomap(node, 0); 245 if (WARN_ON(!gpc_base)) 246 return -ENOMEM; 247 248 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, 249 node, &imx_gpc_domain_ops, 250 NULL); 251 if (!domain) { 252 iounmap(gpc_base); 253 return -ENOMEM; 254 } 255 256 /* Initially mask all interrupts */ 257 for (i = 0; i < IMR_NUM; i++) 258 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); 259 260 /* 261 * Clear the OF_POPULATED flag set in of_irq_init so that 262 * later the GPC power domain driver will not be skipped. 263 */ 264 of_node_clear_flag(node, OF_POPULATED); 265 266 return 0; 267 } 268 IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); 269 270 void __init imx_gpc_check_dt(void) 271 { 272 struct device_node *np; 273 274 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 275 if (WARN_ON(!np)) 276 return; 277 278 if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) { 279 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 280 281 /* map GPC, so that at least CPUidle and WARs keep working */ 282 gpc_base = of_iomap(np, 0); 283 } 284 of_node_put(np); 285 } 286