1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/irqchip/arm-gic.h> 24 #include "common.h" 25 #include "hardware.h" 26 27 #define GPC_CNTR 0x000 28 #define GPC_IMR1 0x008 29 #define GPC_PGC_GPU_PDN 0x260 30 #define GPC_PGC_GPU_PUPSCR 0x264 31 #define GPC_PGC_GPU_PDNSCR 0x268 32 #define GPC_PGC_CPU_PDN 0x2a0 33 #define GPC_PGC_CPU_PUPSCR 0x2a4 34 #define GPC_PGC_CPU_PDNSCR 0x2a8 35 #define GPC_PGC_SW2ISO_SHIFT 0x8 36 #define GPC_PGC_SW_SHIFT 0x0 37 38 #define IMR_NUM 4 39 40 #define GPU_VPU_PUP_REQ BIT(1) 41 #define GPU_VPU_PDN_REQ BIT(0) 42 43 #define GPC_CLK_MAX 6 44 45 struct pu_domain { 46 struct generic_pm_domain base; 47 struct regulator *reg; 48 struct clk *clk[GPC_CLK_MAX]; 49 int num_clks; 50 }; 51 52 static void __iomem *gpc_base; 53 static u32 gpc_wake_irqs[IMR_NUM]; 54 static u32 gpc_saved_imrs[IMR_NUM]; 55 56 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) 57 { 58 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 59 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); 60 } 61 62 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw) 63 { 64 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 65 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); 66 } 67 68 void imx_gpc_set_arm_power_in_lpm(bool power_off) 69 { 70 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); 71 } 72 73 void imx_gpc_pre_suspend(bool arm_power_off) 74 { 75 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 76 int i; 77 78 /* Tell GPC to power off ARM core when suspend */ 79 if (arm_power_off) 80 imx_gpc_set_arm_power_in_lpm(arm_power_off); 81 82 for (i = 0; i < IMR_NUM; i++) { 83 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 84 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); 85 } 86 } 87 88 void imx_gpc_post_resume(void) 89 { 90 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 91 int i; 92 93 /* Keep ARM core powered on for other low-power modes */ 94 imx_gpc_set_arm_power_in_lpm(false); 95 96 for (i = 0; i < IMR_NUM; i++) 97 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 98 } 99 100 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) 101 { 102 unsigned int idx = d->hwirq / 32 - 1; 103 u32 mask; 104 105 /* Sanity check for SPI irq */ 106 if (d->hwirq < 32) 107 return -EINVAL; 108 109 mask = 1 << d->hwirq % 32; 110 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : 111 gpc_wake_irqs[idx] & ~mask; 112 113 return 0; 114 } 115 116 void imx_gpc_mask_all(void) 117 { 118 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 119 int i; 120 121 for (i = 0; i < IMR_NUM; i++) { 122 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); 123 writel_relaxed(~0, reg_imr1 + i * 4); 124 } 125 126 } 127 128 void imx_gpc_restore_all(void) 129 { 130 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; 131 int i; 132 133 for (i = 0; i < IMR_NUM; i++) 134 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 135 } 136 137 void imx_gpc_hwirq_unmask(unsigned int hwirq) 138 { 139 void __iomem *reg; 140 u32 val; 141 142 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 143 val = readl_relaxed(reg); 144 val &= ~(1 << hwirq % 32); 145 writel_relaxed(val, reg); 146 } 147 148 void imx_gpc_hwirq_mask(unsigned int hwirq) 149 { 150 void __iomem *reg; 151 u32 val; 152 153 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 154 val = readl_relaxed(reg); 155 val |= 1 << (hwirq % 32); 156 writel_relaxed(val, reg); 157 } 158 159 static void imx_gpc_irq_unmask(struct irq_data *d) 160 { 161 /* Sanity check for SPI irq */ 162 if (d->hwirq < 32) 163 return; 164 165 imx_gpc_hwirq_unmask(d->hwirq); 166 } 167 168 static void imx_gpc_irq_mask(struct irq_data *d) 169 { 170 /* Sanity check for SPI irq */ 171 if (d->hwirq < 32) 172 return; 173 174 imx_gpc_hwirq_mask(d->hwirq); 175 } 176 177 void __init imx_gpc_init(void) 178 { 179 struct device_node *np; 180 int i; 181 182 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 183 gpc_base = of_iomap(np, 0); 184 WARN_ON(!gpc_base); 185 186 /* Initially mask all interrupts */ 187 for (i = 0; i < IMR_NUM; i++) 188 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); 189 190 /* Register GPC as the secondary interrupt controller behind GIC */ 191 gic_arch_extn.irq_mask = imx_gpc_irq_mask; 192 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; 193 gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; 194 } 195 196 #ifdef CONFIG_PM_GENERIC_DOMAINS 197 198 static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) 199 { 200 int iso, iso2sw; 201 u32 val; 202 203 /* Read ISO and ISO2SW power down delays */ 204 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); 205 iso = val & 0x3f; 206 iso2sw = (val >> 8) & 0x3f; 207 208 /* Gate off PU domain when GPU/VPU when powered down */ 209 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); 210 211 /* Request GPC to power down GPU/VPU */ 212 val = readl_relaxed(gpc_base + GPC_CNTR); 213 val |= GPU_VPU_PDN_REQ; 214 writel_relaxed(val, gpc_base + GPC_CNTR); 215 216 /* Wait ISO + ISO2SW IPG clock cycles */ 217 ndelay((iso + iso2sw) * 1000 / 66); 218 } 219 220 static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) 221 { 222 struct pu_domain *pu = container_of(genpd, struct pu_domain, base); 223 224 _imx6q_pm_pu_power_off(genpd); 225 226 if (pu->reg) 227 regulator_disable(pu->reg); 228 229 return 0; 230 } 231 232 static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) 233 { 234 struct pu_domain *pu = container_of(genpd, struct pu_domain, base); 235 int i, ret, sw, sw2iso; 236 u32 val; 237 238 if (pu->reg) 239 ret = regulator_enable(pu->reg); 240 if (pu->reg && ret) { 241 pr_err("%s: failed to enable regulator: %d\n", __func__, ret); 242 return ret; 243 } 244 245 /* Enable reset clocks for all devices in the PU domain */ 246 for (i = 0; i < pu->num_clks; i++) 247 clk_prepare_enable(pu->clk[i]); 248 249 /* Gate off PU domain when GPU/VPU when powered down */ 250 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); 251 252 /* Read ISO and ISO2SW power down delays */ 253 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); 254 sw = val & 0x3f; 255 sw2iso = (val >> 8) & 0x3f; 256 257 /* Request GPC to power up GPU/VPU */ 258 val = readl_relaxed(gpc_base + GPC_CNTR); 259 val |= GPU_VPU_PUP_REQ; 260 writel_relaxed(val, gpc_base + GPC_CNTR); 261 262 /* Wait ISO + ISO2SW IPG clock cycles */ 263 ndelay((sw + sw2iso) * 1000 / 66); 264 265 /* Disable reset clocks for all devices in the PU domain */ 266 for (i = 0; i < pu->num_clks; i++) 267 clk_disable_unprepare(pu->clk[i]); 268 269 return 0; 270 } 271 272 static struct generic_pm_domain imx6q_arm_domain = { 273 .name = "ARM", 274 }; 275 276 static struct pu_domain imx6q_pu_domain = { 277 .base = { 278 .name = "PU", 279 .power_off = imx6q_pm_pu_power_off, 280 .power_on = imx6q_pm_pu_power_on, 281 .power_off_latency_ns = 25000, 282 .power_on_latency_ns = 2000000, 283 }, 284 }; 285 286 static struct generic_pm_domain imx6sl_display_domain = { 287 .name = "DISPLAY", 288 }; 289 290 static struct generic_pm_domain *imx_gpc_domains[] = { 291 &imx6q_arm_domain, 292 &imx6q_pu_domain.base, 293 &imx6sl_display_domain, 294 }; 295 296 static struct genpd_onecell_data imx_gpc_onecell_data = { 297 .domains = imx_gpc_domains, 298 .num_domains = ARRAY_SIZE(imx_gpc_domains), 299 }; 300 301 static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) 302 { 303 struct clk *clk; 304 bool is_off; 305 int i; 306 307 imx6q_pu_domain.reg = pu_reg; 308 309 for (i = 0; ; i++) { 310 clk = of_clk_get(dev->of_node, i); 311 if (IS_ERR(clk)) 312 break; 313 if (i >= GPC_CLK_MAX) { 314 dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX); 315 goto clk_err; 316 } 317 imx6q_pu_domain.clk[i] = clk; 318 } 319 imx6q_pu_domain.num_clks = i; 320 321 is_off = IS_ENABLED(CONFIG_PM); 322 if (is_off) { 323 _imx6q_pm_pu_power_off(&imx6q_pu_domain.base); 324 } else { 325 /* 326 * Enable power if compiled without CONFIG_PM in case the 327 * bootloader disabled it. 328 */ 329 imx6q_pm_pu_power_on(&imx6q_pu_domain.base); 330 } 331 332 pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off); 333 return of_genpd_add_provider_onecell(dev->of_node, 334 &imx_gpc_onecell_data); 335 336 clk_err: 337 while (i--) 338 clk_put(imx6q_pu_domain.clk[i]); 339 return -EINVAL; 340 } 341 342 #else 343 static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg) 344 { 345 return 0; 346 } 347 #endif /* CONFIG_PM_GENERIC_DOMAINS */ 348 349 static int imx_gpc_probe(struct platform_device *pdev) 350 { 351 struct regulator *pu_reg; 352 int ret; 353 354 pu_reg = devm_regulator_get_optional(&pdev->dev, "pu"); 355 if (PTR_ERR(pu_reg) == -ENODEV) 356 pu_reg = NULL; 357 if (IS_ERR(pu_reg)) { 358 ret = PTR_ERR(pu_reg); 359 dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret); 360 return ret; 361 } 362 363 return imx_gpc_genpd_init(&pdev->dev, pu_reg); 364 } 365 366 static const struct of_device_id imx_gpc_dt_ids[] = { 367 { .compatible = "fsl,imx6q-gpc" }, 368 { .compatible = "fsl,imx6sl-gpc" }, 369 { } 370 }; 371 372 static struct platform_driver imx_gpc_driver = { 373 .driver = { 374 .name = "imx-gpc", 375 .owner = THIS_MODULE, 376 .of_match_table = imx_gpc_dt_ids, 377 }, 378 .probe = imx_gpc_probe, 379 }; 380 381 static int __init imx_pgc_init(void) 382 { 383 return platform_driver_register(&imx_gpc_driver); 384 } 385 subsys_initcall(imx_pgc_init); 386