116216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 229781fa6SFabio Estevam /* 329781fa6SFabio Estevam * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 429781fa6SFabio Estevam * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 529781fa6SFabio Estevam */ 629781fa6SFabio Estevam 729781fa6SFabio Estevam #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 829781fa6SFabio Estevam #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 929781fa6SFabio Estevam 1029781fa6SFabio Estevam #define CKIH_CLK_FREQ 26000000 1129781fa6SFabio Estevam #define CKIH_CLK_FREQ_27MHZ 27000000 1229781fa6SFabio Estevam #define CKIL_CLK_FREQ 32768 1329781fa6SFabio Estevam 14eb92044eSSascha Hauer extern void __iomem *mx3_ccm_base; 1529781fa6SFabio Estevam 1629781fa6SFabio Estevam /* Register addresses */ 17eb92044eSSascha Hauer #define MXC_CCM_CCMR 0x00 18eb92044eSSascha Hauer #define MXC_CCM_PDR0 0x04 19eb92044eSSascha Hauer #define MXC_CCM_PDR1 0x08 20eb92044eSSascha Hauer #define MX35_CCM_PDR2 0x0C 21eb92044eSSascha Hauer #define MXC_CCM_RCSR 0x0C 22eb92044eSSascha Hauer #define MX35_CCM_PDR3 0x10 23eb92044eSSascha Hauer #define MXC_CCM_MPCTL 0x10 24eb92044eSSascha Hauer #define MX35_CCM_PDR4 0x14 25eb92044eSSascha Hauer #define MXC_CCM_UPCTL 0x14 26eb92044eSSascha Hauer #define MX35_CCM_RCSR 0x18 27eb92044eSSascha Hauer #define MXC_CCM_SRPCTL 0x18 28eb92044eSSascha Hauer #define MX35_CCM_MPCTL 0x1C 29eb92044eSSascha Hauer #define MXC_CCM_COSR 0x1C 30eb92044eSSascha Hauer #define MX35_CCM_PPCTL 0x20 31eb92044eSSascha Hauer #define MXC_CCM_CGR0 0x20 32eb92044eSSascha Hauer #define MX35_CCM_ACMR 0x24 33eb92044eSSascha Hauer #define MXC_CCM_CGR1 0x24 34eb92044eSSascha Hauer #define MX35_CCM_COSR 0x28 35eb92044eSSascha Hauer #define MXC_CCM_CGR2 0x28 36eb92044eSSascha Hauer #define MX35_CCM_CGR0 0x2C 37eb92044eSSascha Hauer #define MXC_CCM_WIMR 0x2C 38eb92044eSSascha Hauer #define MX35_CCM_CGR1 0x30 39eb92044eSSascha Hauer #define MXC_CCM_LDC 0x30 40eb92044eSSascha Hauer #define MX35_CCM_CGR2 0x34 41eb92044eSSascha Hauer #define MXC_CCM_DCVR0 0x34 42eb92044eSSascha Hauer #define MX35_CCM_CGR3 0x38 43eb92044eSSascha Hauer #define MXC_CCM_DCVR1 0x38 44eb92044eSSascha Hauer #define MXC_CCM_DCVR2 0x3C 45eb92044eSSascha Hauer #define MXC_CCM_DCVR3 0x40 46eb92044eSSascha Hauer #define MXC_CCM_LTR0 0x44 47eb92044eSSascha Hauer #define MXC_CCM_LTR1 0x48 48eb92044eSSascha Hauer #define MXC_CCM_LTR2 0x4C 49eb92044eSSascha Hauer #define MXC_CCM_LTR3 0x50 50eb92044eSSascha Hauer #define MXC_CCM_LTBR0 0x54 51eb92044eSSascha Hauer #define MXC_CCM_LTBR1 0x58 52eb92044eSSascha Hauer #define MXC_CCM_PMCR0 0x5C 53eb92044eSSascha Hauer #define MXC_CCM_PMCR1 0x60 54eb92044eSSascha Hauer #define MXC_CCM_PDR2 0x64 5529781fa6SFabio Estevam 5629781fa6SFabio Estevam /* Register bit definitions */ 5729781fa6SFabio Estevam #define MXC_CCM_CCMR_WBEN (1 << 27) 5829781fa6SFabio Estevam #define MXC_CCM_CCMR_CSCS (1 << 25) 5929781fa6SFabio Estevam #define MXC_CCM_CCMR_PERCS (1 << 24) 6029781fa6SFabio Estevam #define MXC_CCM_CCMR_SSI1S_OFFSET 18 6129781fa6SFabio Estevam #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) 6229781fa6SFabio Estevam #define MXC_CCM_CCMR_SSI2S_OFFSET 21 6329781fa6SFabio Estevam #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 6429781fa6SFabio Estevam #define MXC_CCM_CCMR_LPM_OFFSET 14 6529781fa6SFabio Estevam #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 66281b0539SLinus Torvalds #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) 6729781fa6SFabio Estevam #define MXC_CCM_CCMR_FIRS_OFFSET 11 6829781fa6SFabio Estevam #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 6929781fa6SFabio Estevam #define MXC_CCM_CCMR_UPE (1 << 9) 7029781fa6SFabio Estevam #define MXC_CCM_CCMR_SPE (1 << 8) 7129781fa6SFabio Estevam #define MXC_CCM_CCMR_MDS (1 << 7) 7229781fa6SFabio Estevam #define MXC_CCM_CCMR_SBYCS (1 << 4) 7329781fa6SFabio Estevam #define MXC_CCM_CCMR_MPE (1 << 3) 7429781fa6SFabio Estevam #define MXC_CCM_CCMR_PRCS_OFFSET 1 7529781fa6SFabio Estevam #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) 7629781fa6SFabio Estevam 7729781fa6SFabio Estevam #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 7829781fa6SFabio Estevam #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) 7929781fa6SFabio Estevam #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 8029781fa6SFabio Estevam #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) 8129781fa6SFabio Estevam #define MXC_CCM_PDR0_PER_PODF_OFFSET 16 8229781fa6SFabio Estevam #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) 8329781fa6SFabio Estevam #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 8429781fa6SFabio Estevam #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) 8529781fa6SFabio Estevam #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 8629781fa6SFabio Estevam #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) 8729781fa6SFabio Estevam #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 8829781fa6SFabio Estevam #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) 8929781fa6SFabio Estevam #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 9029781fa6SFabio Estevam #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) 9129781fa6SFabio Estevam #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 9229781fa6SFabio Estevam #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 9329781fa6SFabio Estevam 9429781fa6SFabio Estevam #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 9529781fa6SFabio Estevam #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 9629781fa6SFabio Estevam #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 9729781fa6SFabio Estevam #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) 9829781fa6SFabio Estevam #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 9929781fa6SFabio Estevam #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) 10029781fa6SFabio Estevam #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 10129781fa6SFabio Estevam #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) 10229781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 10329781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) 10429781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 10529781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) 10629781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 10729781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) 10829781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 10929781fa6SFabio Estevam #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F 11029781fa6SFabio Estevam 11129781fa6SFabio Estevam /* Bit definitions for RCSR */ 11229781fa6SFabio Estevam #define MXC_CCM_RCSR_NF16B 0x80000000 11329781fa6SFabio Estevam 11429781fa6SFabio Estevam /* 11529781fa6SFabio Estevam * LTR0 register offsets 11629781fa6SFabio Estevam */ 11729781fa6SFabio Estevam #define MXC_CCM_LTR0_DIV3CK_OFFSET 1 11829781fa6SFabio Estevam #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) 11929781fa6SFabio Estevam #define MXC_CCM_LTR0_DNTHR_OFFSET 16 12029781fa6SFabio Estevam #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) 12129781fa6SFabio Estevam #define MXC_CCM_LTR0_UPTHR_OFFSET 22 12229781fa6SFabio Estevam #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) 12329781fa6SFabio Estevam 12429781fa6SFabio Estevam /* 12529781fa6SFabio Estevam * LTR1 register offsets 12629781fa6SFabio Estevam */ 12729781fa6SFabio Estevam #define MXC_CCM_LTR1_PNCTHR_OFFSET 0 12829781fa6SFabio Estevam #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F 12929781fa6SFabio Estevam #define MXC_CCM_LTR1_UPCNT_OFFSET 6 13029781fa6SFabio Estevam #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) 13129781fa6SFabio Estevam #define MXC_CCM_LTR1_DNCNT_OFFSET 14 13229781fa6SFabio Estevam #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) 13329781fa6SFabio Estevam #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 13429781fa6SFabio Estevam #define MXC_CCM_LTR1_LTBRSR_OFFSET 22 13529781fa6SFabio Estevam #define MXC_CCM_LTR1_LTBRSR 0x400000 13629781fa6SFabio Estevam #define MXC_CCM_LTR1_LTBRSH 0x800000 13729781fa6SFabio Estevam 13829781fa6SFabio Estevam /* 13929781fa6SFabio Estevam * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 14029781fa6SFabio Estevam */ 14129781fa6SFabio Estevam #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) 14229781fa6SFabio Estevam #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ 14329781fa6SFabio Estevam MXC_CCM_LTR2_WSW_OFFSET((x))) 14429781fa6SFabio Estevam #define MXC_CCM_LTR2_EMAC_OFFSET 0 14529781fa6SFabio Estevam #define MXC_CCM_LTR2_EMAC_MASK 0x1FF 14629781fa6SFabio Estevam 14729781fa6SFabio Estevam /* 14829781fa6SFabio Estevam * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 14929781fa6SFabio Estevam */ 15029781fa6SFabio Estevam #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) 15129781fa6SFabio Estevam #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ 15229781fa6SFabio Estevam MXC_CCM_LTR3_WSW_OFFSET((x))) 15329781fa6SFabio Estevam 15429781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP1 0x80000000 15529781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) 15629781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) 15729781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP0 0x40000000 15829781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) 15929781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) 16029781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) 16129781fa6SFabio Estevam 16229781fa6SFabio Estevam #define DVSUP_TURBO 0 16329781fa6SFabio Estevam #define DVSUP_HIGH 1 16429781fa6SFabio Estevam #define DVSUP_MEDIUM 2 16529781fa6SFabio Estevam #define DVSUP_LOW 3 16629781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) 16729781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) 16829781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) 16929781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) 17029781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_OFFSET 28 17129781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) 17229781fa6SFabio Estevam #define MXC_CCM_PMCR0_UDSC 0x08000000 17329781fa6SFabio Estevam #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) 17429781fa6SFabio Estevam #define MXC_CCM_PMCR0_UDSC_UP (1 << 27) 17529781fa6SFabio Estevam #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) 17629781fa6SFabio Estevam 17729781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) 17829781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) 17929781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) 18029781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) 18129781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) 18229781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) 18329781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) 18429781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) 18529781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_OFFSET 24 18629781fa6SFabio Estevam #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) 18729781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVFEV 0x00800000 18829781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVFIS 0x00400000 18929781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBMI 0x00200000 19029781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBFL 0x00100000 19129781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) 19229781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) 19329781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) 19429781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) 19529781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_OFFSET 18 19629781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) 19729781fa6SFabio Estevam #define MXC_CCM_PMCR0_PTVIS 0x00020000 19829781fa6SFabio Estevam #define MXC_CCM_PMCR0_UPDTEN 0x00010000 19929781fa6SFabio Estevam #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) 20029781fa6SFabio Estevam #define MXC_CCM_PMCR0_FSVAIM 0x00008000 20129781fa6SFabio Estevam #define MXC_CCM_PMCR0_FSVAI_OFFSET 13 20229781fa6SFabio Estevam #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) 20329781fa6SFabio Estevam #define MXC_CCM_PMCR0_DPVCR 0x00001000 20429781fa6SFabio Estevam #define MXC_CCM_PMCR0_DPVV 0x00000800 20529781fa6SFabio Estevam #define MXC_CCM_PMCR0_WFIM 0x00000400 20629781fa6SFabio Estevam #define MXC_CCM_PMCR0_DRCE3 0x00000200 20729781fa6SFabio Estevam #define MXC_CCM_PMCR0_DRCE2 0x00000100 20829781fa6SFabio Estevam #define MXC_CCM_PMCR0_DRCE1 0x00000080 20929781fa6SFabio Estevam #define MXC_CCM_PMCR0_DRCE0 0x00000040 21029781fa6SFabio Estevam #define MXC_CCM_PMCR0_DCR 0x00000020 21129781fa6SFabio Estevam #define MXC_CCM_PMCR0_DVFEN 0x00000010 21229781fa6SFabio Estevam #define MXC_CCM_PMCR0_PTVAIM 0x00000008 21329781fa6SFabio Estevam #define MXC_CCM_PMCR0_PTVAI_OFFSET 1 21429781fa6SFabio Estevam #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) 21529781fa6SFabio Estevam #define MXC_CCM_PMCR0_DPTEN 0x00000001 21629781fa6SFabio Estevam 21729781fa6SFabio Estevam #define MXC_CCM_PMCR1_DVGP_OFFSET 0 21829781fa6SFabio Estevam #define MXC_CCM_PMCR1_DVGP_MASK (0xF) 21929781fa6SFabio Estevam 22029781fa6SFabio Estevam #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) 22129781fa6SFabio Estevam #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) 22229781fa6SFabio Estevam 22329781fa6SFabio Estevam #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) 22429781fa6SFabio Estevam #define MXC_CCM_DCVR_ULV_OFFSET 22 22529781fa6SFabio Estevam #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) 22629781fa6SFabio Estevam #define MXC_CCM_DCVR_LLV_OFFSET 12 22729781fa6SFabio Estevam #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) 22829781fa6SFabio Estevam #define MXC_CCM_DCVR_ELV_OFFSET 2 22929781fa6SFabio Estevam 23029781fa6SFabio Estevam #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) 23129781fa6SFabio Estevam #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 23229781fa6SFabio Estevam #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F 23329781fa6SFabio Estevam #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 23429781fa6SFabio Estevam 23529781fa6SFabio Estevam #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F 23629781fa6SFabio Estevam #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 23729781fa6SFabio Estevam #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) 23829781fa6SFabio Estevam #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 23929781fa6SFabio Estevam #define MXC_CCM_COSR_CLKOEN (1 << 9) 24029781fa6SFabio Estevam 24129781fa6SFabio Estevam /* 24229781fa6SFabio Estevam * PMCR0 register offsets 24329781fa6SFabio Estevam */ 24429781fa6SFabio Estevam #define MXC_CCM_PMCR0_LBFL_OFFSET 20 24529781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 24629781fa6SFabio Estevam #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 24729781fa6SFabio Estevam 24829781fa6SFabio Estevam #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ 249