1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/err.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/module.h> 5 #include <linux/io.h> 6 #include <linux/of.h> 7 #include <linux/of_address.h> 8 #include <linux/regmap.h> 9 #include <linux/slab.h> 10 #include <linux/sys_soc.h> 11 12 #include "hardware.h" 13 #include "common.h" 14 15 #define OCOTP_UID_H 0x420 16 #define OCOTP_UID_L 0x410 17 18 #define OCOTP_ULP_UID_1 0x4b0 19 #define OCOTP_ULP_UID_2 0x4c0 20 #define OCOTP_ULP_UID_3 0x4d0 21 #define OCOTP_ULP_UID_4 0x4e0 22 23 unsigned int __mxc_cpu_type; 24 static unsigned int imx_soc_revision; 25 26 void mxc_set_cpu_type(unsigned int type) 27 { 28 __mxc_cpu_type = type; 29 } 30 31 void imx_set_soc_revision(unsigned int rev) 32 { 33 imx_soc_revision = rev; 34 } 35 36 unsigned int imx_get_soc_revision(void) 37 { 38 return imx_soc_revision; 39 } 40 41 void imx_print_silicon_rev(const char *cpu, int srev) 42 { 43 if (srev == IMX_CHIP_REVISION_UNKNOWN) 44 pr_info("CPU identified as %s, unknown revision\n", cpu); 45 else 46 pr_info("CPU identified as %s, silicon rev %d.%d\n", 47 cpu, (srev >> 4) & 0xf, srev & 0xf); 48 } 49 50 void __init imx_set_aips(void __iomem *base) 51 { 52 unsigned int reg; 53 /* 54 * Set all MPROTx to be non-bufferable, trusted for R/W, 55 * not forced to user-mode. 56 */ 57 imx_writel(0x77777777, base + 0x0); 58 imx_writel(0x77777777, base + 0x4); 59 60 /* 61 * Set all OPACRx to be non-bufferable, to not require 62 * supervisor privilege level for access, allow for 63 * write access and untrusted master access. 64 */ 65 imx_writel(0x0, base + 0x40); 66 imx_writel(0x0, base + 0x44); 67 imx_writel(0x0, base + 0x48); 68 imx_writel(0x0, base + 0x4C); 69 reg = imx_readl(base + 0x50) & 0x00FFFFFF; 70 imx_writel(reg, base + 0x50); 71 } 72 73 void __init imx_aips_allow_unprivileged_access( 74 const char *compat) 75 { 76 void __iomem *aips_base_addr; 77 struct device_node *np; 78 79 for_each_compatible_node(np, NULL, compat) { 80 aips_base_addr = of_iomap(np, 0); 81 WARN_ON(!aips_base_addr); 82 imx_set_aips(aips_base_addr); 83 } 84 } 85 86 struct device * __init imx_soc_device_init(void) 87 { 88 struct soc_device_attribute *soc_dev_attr; 89 const char *ocotp_compat = NULL; 90 struct soc_device *soc_dev; 91 struct device_node *root; 92 struct regmap *ocotp = NULL; 93 const char *soc_id; 94 u64 soc_uid = 0; 95 u32 val; 96 int ret; 97 98 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 99 if (!soc_dev_attr) 100 return NULL; 101 102 soc_dev_attr->family = "Freescale i.MX"; 103 104 root = of_find_node_by_path("/"); 105 ret = of_property_read_string(root, "model", &soc_dev_attr->machine); 106 of_node_put(root); 107 if (ret) 108 goto free_soc; 109 110 switch (__mxc_cpu_type) { 111 case MXC_CPU_MX1: 112 soc_id = "i.MX1"; 113 break; 114 case MXC_CPU_MX21: 115 soc_id = "i.MX21"; 116 break; 117 case MXC_CPU_MX25: 118 soc_id = "i.MX25"; 119 break; 120 case MXC_CPU_MX27: 121 soc_id = "i.MX27"; 122 break; 123 case MXC_CPU_MX31: 124 soc_id = "i.MX31"; 125 break; 126 case MXC_CPU_MX35: 127 soc_id = "i.MX35"; 128 break; 129 case MXC_CPU_MX51: 130 soc_id = "i.MX51"; 131 break; 132 case MXC_CPU_MX53: 133 soc_id = "i.MX53"; 134 break; 135 case MXC_CPU_IMX6SL: 136 ocotp_compat = "fsl,imx6sl-ocotp"; 137 soc_id = "i.MX6SL"; 138 break; 139 case MXC_CPU_IMX6DL: 140 ocotp_compat = "fsl,imx6q-ocotp"; 141 soc_id = "i.MX6DL"; 142 break; 143 case MXC_CPU_IMX6SX: 144 ocotp_compat = "fsl,imx6sx-ocotp"; 145 soc_id = "i.MX6SX"; 146 break; 147 case MXC_CPU_IMX6Q: 148 ocotp_compat = "fsl,imx6q-ocotp"; 149 soc_id = "i.MX6Q"; 150 break; 151 case MXC_CPU_IMX6UL: 152 ocotp_compat = "fsl,imx6ul-ocotp"; 153 soc_id = "i.MX6UL"; 154 break; 155 case MXC_CPU_IMX6ULL: 156 ocotp_compat = "fsl,imx6ull-ocotp"; 157 soc_id = "i.MX6ULL"; 158 break; 159 case MXC_CPU_IMX6ULZ: 160 ocotp_compat = "fsl,imx6ull-ocotp"; 161 soc_id = "i.MX6ULZ"; 162 break; 163 case MXC_CPU_IMX6SLL: 164 ocotp_compat = "fsl,imx6sll-ocotp"; 165 soc_id = "i.MX6SLL"; 166 break; 167 case MXC_CPU_IMX7D: 168 ocotp_compat = "fsl,imx7d-ocotp"; 169 soc_id = "i.MX7D"; 170 break; 171 case MXC_CPU_IMX7ULP: 172 ocotp_compat = "fsl,imx7ulp-ocotp"; 173 soc_id = "i.MX7ULP"; 174 break; 175 default: 176 soc_id = "Unknown"; 177 } 178 soc_dev_attr->soc_id = soc_id; 179 180 if (ocotp_compat) { 181 ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat); 182 if (IS_ERR(ocotp)) 183 pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat); 184 } 185 186 if (!IS_ERR_OR_NULL(ocotp)) { 187 if (__mxc_cpu_type == MXC_CPU_IMX7ULP) { 188 regmap_read(ocotp, OCOTP_ULP_UID_4, &val); 189 soc_uid = val & 0xffff; 190 regmap_read(ocotp, OCOTP_ULP_UID_3, &val); 191 soc_uid <<= 16; 192 soc_uid |= val & 0xffff; 193 regmap_read(ocotp, OCOTP_ULP_UID_2, &val); 194 soc_uid <<= 16; 195 soc_uid |= val & 0xffff; 196 regmap_read(ocotp, OCOTP_ULP_UID_1, &val); 197 soc_uid <<= 16; 198 soc_uid |= val & 0xffff; 199 } else { 200 regmap_read(ocotp, OCOTP_UID_H, &val); 201 soc_uid = val; 202 regmap_read(ocotp, OCOTP_UID_L, &val); 203 soc_uid <<= 32; 204 soc_uid |= val; 205 } 206 } 207 208 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", 209 (imx_soc_revision >> 4) & 0xf, 210 imx_soc_revision & 0xf); 211 if (!soc_dev_attr->revision) 212 goto free_soc; 213 214 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); 215 if (!soc_dev_attr->serial_number) 216 goto free_rev; 217 218 soc_dev = soc_device_register(soc_dev_attr); 219 if (IS_ERR(soc_dev)) 220 goto free_serial_number; 221 222 return soc_device_to_device(soc_dev); 223 224 free_serial_number: 225 kfree(soc_dev_attr->serial_number); 226 free_rev: 227 kfree(soc_dev_attr->revision); 228 free_soc: 229 kfree(soc_dev_attr); 230 return NULL; 231 } 232