1 #include <linux/err.h> 2 #include <linux/module.h> 3 #include <linux/io.h> 4 #include <linux/of.h> 5 #include <linux/slab.h> 6 #include <linux/sys_soc.h> 7 8 #include "hardware.h" 9 #include "common.h" 10 11 unsigned int __mxc_cpu_type; 12 EXPORT_SYMBOL(__mxc_cpu_type); 13 14 static unsigned int imx_soc_revision; 15 16 void mxc_set_cpu_type(unsigned int type) 17 { 18 __mxc_cpu_type = type; 19 } 20 21 void imx_set_soc_revision(unsigned int rev) 22 { 23 imx_soc_revision = rev; 24 } 25 26 unsigned int imx_get_soc_revision(void) 27 { 28 return imx_soc_revision; 29 } 30 31 void imx_print_silicon_rev(const char *cpu, int srev) 32 { 33 if (srev == IMX_CHIP_REVISION_UNKNOWN) 34 pr_info("CPU identified as %s, unknown revision\n", cpu); 35 else 36 pr_info("CPU identified as %s, silicon rev %d.%d\n", 37 cpu, (srev >> 4) & 0xf, srev & 0xf); 38 } 39 40 void __init imx_set_aips(void __iomem *base) 41 { 42 unsigned int reg; 43 /* 44 * Set all MPROTx to be non-bufferable, trusted for R/W, 45 * not forced to user-mode. 46 */ 47 __raw_writel(0x77777777, base + 0x0); 48 __raw_writel(0x77777777, base + 0x4); 49 50 /* 51 * Set all OPACRx to be non-bufferable, to not require 52 * supervisor privilege level for access, allow for 53 * write access and untrusted master access. 54 */ 55 __raw_writel(0x0, base + 0x40); 56 __raw_writel(0x0, base + 0x44); 57 __raw_writel(0x0, base + 0x48); 58 __raw_writel(0x0, base + 0x4C); 59 reg = __raw_readl(base + 0x50) & 0x00FFFFFF; 60 __raw_writel(reg, base + 0x50); 61 } 62 63 struct device * __init imx_soc_device_init(void) 64 { 65 struct soc_device_attribute *soc_dev_attr; 66 struct soc_device *soc_dev; 67 struct device_node *root; 68 const char *soc_id; 69 int ret; 70 71 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 72 if (!soc_dev_attr) 73 return NULL; 74 75 soc_dev_attr->family = "Freescale i.MX"; 76 77 root = of_find_node_by_path("/"); 78 ret = of_property_read_string(root, "model", &soc_dev_attr->machine); 79 of_node_put(root); 80 if (ret) 81 goto free_soc; 82 83 switch (__mxc_cpu_type) { 84 case MXC_CPU_MX1: 85 soc_id = "i.MX1"; 86 break; 87 case MXC_CPU_MX21: 88 soc_id = "i.MX21"; 89 break; 90 case MXC_CPU_MX25: 91 soc_id = "i.MX25"; 92 break; 93 case MXC_CPU_MX27: 94 soc_id = "i.MX27"; 95 break; 96 case MXC_CPU_MX31: 97 soc_id = "i.MX31"; 98 break; 99 case MXC_CPU_MX35: 100 soc_id = "i.MX35"; 101 break; 102 case MXC_CPU_MX51: 103 soc_id = "i.MX51"; 104 break; 105 case MXC_CPU_MX53: 106 soc_id = "i.MX53"; 107 break; 108 case MXC_CPU_IMX6SL: 109 soc_id = "i.MX6SL"; 110 break; 111 case MXC_CPU_IMX6DL: 112 soc_id = "i.MX6DL"; 113 break; 114 case MXC_CPU_IMX6SX: 115 soc_id = "i.MX6SX"; 116 break; 117 case MXC_CPU_IMX6Q: 118 soc_id = "i.MX6Q"; 119 break; 120 default: 121 soc_id = "Unknown"; 122 } 123 soc_dev_attr->soc_id = soc_id; 124 125 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", 126 (imx_soc_revision >> 4) & 0xf, 127 imx_soc_revision & 0xf); 128 if (!soc_dev_attr->revision) 129 goto free_soc; 130 131 soc_dev = soc_device_register(soc_dev_attr); 132 if (IS_ERR(soc_dev)) 133 goto free_rev; 134 135 return soc_device_to_device(soc_dev); 136 137 free_rev: 138 kfree(soc_dev_attr->revision); 139 free_soc: 140 kfree(soc_dev_attr); 141 return NULL; 142 } 143