1784a90c0SSascha Hauer /* 2784a90c0SSascha Hauer * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 3784a90c0SSascha Hauer * 4784a90c0SSascha Hauer * The code contained herein is licensed under the GNU General Public 5784a90c0SSascha Hauer * License. You may obtain a copy of the GNU General Public License 6784a90c0SSascha Hauer * Version 2 or later at the following locations: 7784a90c0SSascha Hauer * 8784a90c0SSascha Hauer * http://www.opensource.org/licenses/gpl-license.html 9784a90c0SSascha Hauer * http://www.gnu.org/copyleft/gpl.html 10784a90c0SSascha Hauer * 11784a90c0SSascha Hauer * This file contains the CPU initialization code. 12784a90c0SSascha Hauer */ 13784a90c0SSascha Hauer 14784a90c0SSascha Hauer #include <linux/types.h> 15784a90c0SSascha Hauer #include <linux/kernel.h> 16784a90c0SSascha Hauer #include <linux/init.h> 17784a90c0SSascha Hauer #include <linux/module.h> 18eaed435aSLinus Torvalds #include <linux/io.h> 19784a90c0SSascha Hauer 2050f2de61SShawn Guo #include "hardware.h" 2122567796SFabio Estevam #include "common.h" 2250f2de61SShawn Guo 23784a90c0SSascha Hauer static int mx5_cpu_rev = -1; 24784a90c0SSascha Hauer 25784a90c0SSascha Hauer #define IIM_SREV 0x24 26784a90c0SSascha Hauer 27784a90c0SSascha Hauer static int get_mx51_srev(void) 28784a90c0SSascha Hauer { 29784a90c0SSascha Hauer void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); 30784a90c0SSascha Hauer u32 rev = readl(iim_base + IIM_SREV) & 0xff; 31784a90c0SSascha Hauer 32784a90c0SSascha Hauer switch (rev) { 33784a90c0SSascha Hauer case 0x0: 34784a90c0SSascha Hauer return IMX_CHIP_REVISION_2_0; 35784a90c0SSascha Hauer case 0x10: 36784a90c0SSascha Hauer return IMX_CHIP_REVISION_3_0; 37784a90c0SSascha Hauer default: 38784a90c0SSascha Hauer return IMX_CHIP_REVISION_UNKNOWN; 39784a90c0SSascha Hauer } 40784a90c0SSascha Hauer } 41784a90c0SSascha Hauer 42784a90c0SSascha Hauer /* 43784a90c0SSascha Hauer * Returns: 44784a90c0SSascha Hauer * the silicon revision of the cpu 45784a90c0SSascha Hauer * -EINVAL - not a mx51 46784a90c0SSascha Hauer */ 47784a90c0SSascha Hauer int mx51_revision(void) 48784a90c0SSascha Hauer { 49784a90c0SSascha Hauer if (!cpu_is_mx51()) 50784a90c0SSascha Hauer return -EINVAL; 51784a90c0SSascha Hauer 52784a90c0SSascha Hauer if (mx5_cpu_rev == -1) 53784a90c0SSascha Hauer mx5_cpu_rev = get_mx51_srev(); 54784a90c0SSascha Hauer 55784a90c0SSascha Hauer return mx5_cpu_rev; 56784a90c0SSascha Hauer } 57784a90c0SSascha Hauer EXPORT_SYMBOL(mx51_revision); 58784a90c0SSascha Hauer 59784a90c0SSascha Hauer #ifdef CONFIG_NEON 60784a90c0SSascha Hauer 61784a90c0SSascha Hauer /* 62784a90c0SSascha Hauer * All versions of the silicon before Rev. 3 have broken NEON implementations. 63784a90c0SSascha Hauer * Dependent on link order - so the assumption is that vfp_init is called 64784a90c0SSascha Hauer * before us. 65784a90c0SSascha Hauer */ 668321b758SShawn Guo int __init mx51_neon_fixup(void) 67784a90c0SSascha Hauer { 68eaed435aSLinus Torvalds if (mx51_revision() < IMX_CHIP_REVISION_3_0 && 69eaed435aSLinus Torvalds (elf_hwcap & HWCAP_NEON)) { 70784a90c0SSascha Hauer elf_hwcap &= ~HWCAP_NEON; 71784a90c0SSascha Hauer pr_info("Turning off NEON support, detected broken NEON implementation\n"); 72784a90c0SSascha Hauer } 73784a90c0SSascha Hauer return 0; 74784a90c0SSascha Hauer } 75784a90c0SSascha Hauer 76784a90c0SSascha Hauer #endif 77784a90c0SSascha Hauer 78784a90c0SSascha Hauer static int get_mx53_srev(void) 79784a90c0SSascha Hauer { 80784a90c0SSascha Hauer void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); 81784a90c0SSascha Hauer u32 rev = readl(iim_base + IIM_SREV) & 0xff; 82784a90c0SSascha Hauer 83784a90c0SSascha Hauer switch (rev) { 84784a90c0SSascha Hauer case 0x0: 85784a90c0SSascha Hauer return IMX_CHIP_REVISION_1_0; 86784a90c0SSascha Hauer case 0x2: 87784a90c0SSascha Hauer return IMX_CHIP_REVISION_2_0; 88784a90c0SSascha Hauer case 0x3: 89784a90c0SSascha Hauer return IMX_CHIP_REVISION_2_1; 90784a90c0SSascha Hauer default: 91784a90c0SSascha Hauer return IMX_CHIP_REVISION_UNKNOWN; 92784a90c0SSascha Hauer } 93784a90c0SSascha Hauer } 94784a90c0SSascha Hauer 95784a90c0SSascha Hauer /* 96784a90c0SSascha Hauer * Returns: 97784a90c0SSascha Hauer * the silicon revision of the cpu 98784a90c0SSascha Hauer * -EINVAL - not a mx53 99784a90c0SSascha Hauer */ 100784a90c0SSascha Hauer int mx53_revision(void) 101784a90c0SSascha Hauer { 102784a90c0SSascha Hauer if (!cpu_is_mx53()) 103784a90c0SSascha Hauer return -EINVAL; 104784a90c0SSascha Hauer 105784a90c0SSascha Hauer if (mx5_cpu_rev == -1) 106784a90c0SSascha Hauer mx5_cpu_rev = get_mx53_srev(); 107784a90c0SSascha Hauer 108784a90c0SSascha Hauer return mx5_cpu_rev; 109784a90c0SSascha Hauer } 110784a90c0SSascha Hauer EXPORT_SYMBOL(mx53_revision); 111