1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <asm/mach/irq.h> 27 #include <asm/exception.h> 28 29 #include "common.h" 30 #include "hardware.h" 31 #include "irq-common.h" 32 33 #define AVIC_INTCNTL 0x00 /* int control reg */ 34 #define AVIC_NIMASK 0x04 /* int mask reg */ 35 #define AVIC_INTENNUM 0x08 /* int enable number reg */ 36 #define AVIC_INTDISNUM 0x0C /* int disable number reg */ 37 #define AVIC_INTENABLEH 0x10 /* int enable reg high */ 38 #define AVIC_INTENABLEL 0x14 /* int enable reg low */ 39 #define AVIC_INTTYPEH 0x18 /* int type reg high */ 40 #define AVIC_INTTYPEL 0x1C /* int type reg low */ 41 #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ 42 #define AVIC_NIVECSR 0x40 /* norm int vector/status */ 43 #define AVIC_FIVECSR 0x44 /* fast int vector/status */ 44 #define AVIC_INTSRCH 0x48 /* int source reg high */ 45 #define AVIC_INTSRCL 0x4C /* int source reg low */ 46 #define AVIC_INTFRCH 0x50 /* int force reg high */ 47 #define AVIC_INTFRCL 0x54 /* int force reg low */ 48 #define AVIC_NIPNDH 0x58 /* norm int pending high */ 49 #define AVIC_NIPNDL 0x5C /* norm int pending low */ 50 #define AVIC_FIPNDH 0x60 /* fast int pending high */ 51 #define AVIC_FIPNDL 0x64 /* fast int pending low */ 52 53 #define AVIC_NUM_IRQS 64 54 55 /* low power interrupt mask registers */ 56 #define MX25_CCM_LPIMR0 0x68 57 #define MX25_CCM_LPIMR1 0x6C 58 59 static void __iomem *avic_base; 60 static void __iomem *mx25_ccm_base; 61 static struct irq_domain *domain; 62 63 #ifdef CONFIG_FIQ 64 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) 65 { 66 unsigned int irqt; 67 68 if (hwirq >= AVIC_NUM_IRQS) 69 return -EINVAL; 70 71 if (hwirq < AVIC_NUM_IRQS / 2) { 72 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); 73 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); 74 } else { 75 hwirq -= AVIC_NUM_IRQS / 2; 76 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); 77 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); 78 } 79 80 return 0; 81 } 82 #endif /* CONFIG_FIQ */ 83 84 85 static struct mxc_extra_irq avic_extra_irq = { 86 #ifdef CONFIG_FIQ 87 .set_irq_fiq = avic_set_irq_fiq, 88 #endif 89 }; 90 91 #ifdef CONFIG_PM 92 static u32 avic_saved_mask_reg[2]; 93 94 static void avic_irq_suspend(struct irq_data *d) 95 { 96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 97 struct irq_chip_type *ct = gc->chip_types; 98 int idx = d->hwirq >> 5; 99 100 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); 101 imx_writel(gc->wake_active, avic_base + ct->regs.mask); 102 103 if (mx25_ccm_base) { 104 u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? 105 MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; 106 /* 107 * The interrupts which are still enabled will be used as wakeup 108 * sources. Allow those interrupts in low-power mode. 109 * The LPIMR registers use 0 to allow an interrupt, the AVIC 110 * registers use 1. 111 */ 112 imx_writel(~gc->wake_active, mx25_ccm_base + offs); 113 } 114 } 115 116 static void avic_irq_resume(struct irq_data *d) 117 { 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 119 struct irq_chip_type *ct = gc->chip_types; 120 int idx = d->hwirq >> 5; 121 122 imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); 123 124 if (mx25_ccm_base) { 125 u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? 126 MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; 127 128 imx_writel(0xffffffff, mx25_ccm_base + offs); 129 } 130 } 131 132 #else 133 #define avic_irq_suspend NULL 134 #define avic_irq_resume NULL 135 #endif 136 137 static __init void avic_init_gc(int idx, unsigned int irq_start) 138 { 139 struct irq_chip_generic *gc; 140 struct irq_chip_type *ct; 141 142 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, 143 handle_level_irq); 144 gc->private = &avic_extra_irq; 145 gc->wake_enabled = IRQ_MSK(32); 146 147 ct = gc->chip_types; 148 ct->chip.irq_mask = irq_gc_mask_clr_bit; 149 ct->chip.irq_unmask = irq_gc_mask_set_bit; 150 ct->chip.irq_ack = irq_gc_mask_clr_bit; 151 ct->chip.irq_set_wake = irq_gc_set_wake; 152 ct->chip.irq_suspend = avic_irq_suspend; 153 ct->chip.irq_resume = avic_irq_resume; 154 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; 155 ct->regs.ack = ct->regs.mask; 156 157 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 158 } 159 160 static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 161 { 162 u32 nivector; 163 164 do { 165 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; 166 if (nivector == 0xffff) 167 break; 168 169 handle_domain_irq(domain, nivector, regs); 170 } while (1); 171 } 172 173 /* 174 * This function initializes the AVIC hardware and disables all the 175 * interrupts. It registers the interrupt enable and disable functions 176 * to the kernel for each interrupt source. 177 */ 178 void __init mxc_init_irq(void __iomem *irqbase) 179 { 180 struct device_node *np; 181 int irq_base; 182 int i; 183 184 avic_base = irqbase; 185 186 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); 187 mx25_ccm_base = of_iomap(np, 0); 188 189 if (mx25_ccm_base) { 190 /* 191 * By default, we mask all interrupts. We set the actual mask 192 * before we go into low-power mode. 193 */ 194 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); 195 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); 196 } 197 198 /* put the AVIC into the reset value with 199 * all interrupts disabled 200 */ 201 imx_writel(0, avic_base + AVIC_INTCNTL); 202 imx_writel(0x1f, avic_base + AVIC_NIMASK); 203 204 /* disable all interrupts */ 205 imx_writel(0, avic_base + AVIC_INTENABLEH); 206 imx_writel(0, avic_base + AVIC_INTENABLEL); 207 208 /* all IRQ no FIQ */ 209 imx_writel(0, avic_base + AVIC_INTTYPEH); 210 imx_writel(0, avic_base + AVIC_INTTYPEL); 211 212 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); 213 WARN_ON(irq_base < 0); 214 215 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); 216 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, 217 &irq_domain_simple_ops, NULL); 218 WARN_ON(!domain); 219 220 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) 221 avic_init_gc(i, irq_base); 222 223 /* Set default priority value (0) for all IRQ's */ 224 for (i = 0; i < 8; i++) 225 imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); 226 227 set_handle_irq(avic_handle_irq); 228 229 #ifdef CONFIG_FIQ 230 /* Initialize FIQ */ 231 init_FIQ(FIQ_START); 232 #endif 233 234 printk(KERN_INFO "MXC IRQ initialized\n"); 235 } 236