116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
23995eb82SShawn Guo /*
33995eb82SShawn Guo * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
43995eb82SShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
53995eb82SShawn Guo */
63995eb82SShawn Guo
73995eb82SShawn Guo #include <linux/module.h>
83995eb82SShawn Guo #include <linux/irq.h>
93995eb82SShawn Guo #include <linux/irqdomain.h>
10e2c1b0ffSSaravana Kannan #include <linux/irqchip.h>
113995eb82SShawn Guo #include <linux/io.h>
123995eb82SShawn Guo #include <linux/of.h>
139b454d16SMartin Kaiser #include <linux/of_address.h>
143995eb82SShawn Guo #include <asm/mach/irq.h>
153995eb82SShawn Guo #include <asm/exception.h>
163995eb82SShawn Guo
17e3372474SShawn Guo #include "common.h"
1850f2de61SShawn Guo #include "hardware.h"
193995eb82SShawn Guo #include "irq-common.h"
203995eb82SShawn Guo
213995eb82SShawn Guo #define AVIC_INTCNTL 0x00 /* int control reg */
223995eb82SShawn Guo #define AVIC_NIMASK 0x04 /* int mask reg */
233995eb82SShawn Guo #define AVIC_INTENNUM 0x08 /* int enable number reg */
243995eb82SShawn Guo #define AVIC_INTDISNUM 0x0C /* int disable number reg */
253995eb82SShawn Guo #define AVIC_INTENABLEH 0x10 /* int enable reg high */
263995eb82SShawn Guo #define AVIC_INTENABLEL 0x14 /* int enable reg low */
273995eb82SShawn Guo #define AVIC_INTTYPEH 0x18 /* int type reg high */
283995eb82SShawn Guo #define AVIC_INTTYPEL 0x1C /* int type reg low */
293995eb82SShawn Guo #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
303995eb82SShawn Guo #define AVIC_NIVECSR 0x40 /* norm int vector/status */
313995eb82SShawn Guo #define AVIC_FIVECSR 0x44 /* fast int vector/status */
323995eb82SShawn Guo #define AVIC_INTSRCH 0x48 /* int source reg high */
333995eb82SShawn Guo #define AVIC_INTSRCL 0x4C /* int source reg low */
343995eb82SShawn Guo #define AVIC_INTFRCH 0x50 /* int force reg high */
353995eb82SShawn Guo #define AVIC_INTFRCL 0x54 /* int force reg low */
363995eb82SShawn Guo #define AVIC_NIPNDH 0x58 /* norm int pending high */
373995eb82SShawn Guo #define AVIC_NIPNDL 0x5C /* norm int pending low */
383995eb82SShawn Guo #define AVIC_FIPNDH 0x60 /* fast int pending high */
393995eb82SShawn Guo #define AVIC_FIPNDL 0x64 /* fast int pending low */
403995eb82SShawn Guo
413995eb82SShawn Guo #define AVIC_NUM_IRQS 64
423995eb82SShawn Guo
439b454d16SMartin Kaiser /* low power interrupt mask registers */
449b454d16SMartin Kaiser #define MX25_CCM_LPIMR0 0x68
459b454d16SMartin Kaiser #define MX25_CCM_LPIMR1 0x6C
469b454d16SMartin Kaiser
47ae00ac76SFabio Estevam static void __iomem *avic_base;
489b454d16SMartin Kaiser static void __iomem *mx25_ccm_base;
493995eb82SShawn Guo static struct irq_domain *domain;
503995eb82SShawn Guo
513995eb82SShawn Guo #ifdef CONFIG_FIQ
avic_set_irq_fiq(unsigned int hwirq,unsigned int type)52d1e1c31cSAlexander Shiyan static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
533995eb82SShawn Guo {
543995eb82SShawn Guo unsigned int irqt;
553995eb82SShawn Guo
56d1e1c31cSAlexander Shiyan if (hwirq >= AVIC_NUM_IRQS)
573995eb82SShawn Guo return -EINVAL;
583995eb82SShawn Guo
59d1e1c31cSAlexander Shiyan if (hwirq < AVIC_NUM_IRQS / 2) {
60d1e1c31cSAlexander Shiyan irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
61d1e1c31cSAlexander Shiyan imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
623995eb82SShawn Guo } else {
63d1e1c31cSAlexander Shiyan hwirq -= AVIC_NUM_IRQS / 2;
64d1e1c31cSAlexander Shiyan irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
65d1e1c31cSAlexander Shiyan imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
663995eb82SShawn Guo }
673995eb82SShawn Guo
683995eb82SShawn Guo return 0;
693995eb82SShawn Guo }
703995eb82SShawn Guo #endif /* CONFIG_FIQ */
713995eb82SShawn Guo
723995eb82SShawn Guo
733995eb82SShawn Guo static struct mxc_extra_irq avic_extra_irq = {
743995eb82SShawn Guo #ifdef CONFIG_FIQ
753995eb82SShawn Guo .set_irq_fiq = avic_set_irq_fiq,
763995eb82SShawn Guo #endif
773995eb82SShawn Guo };
783995eb82SShawn Guo
793995eb82SShawn Guo #ifdef CONFIG_PM
805fe839d9SFabio Estevam static u32 avic_saved_mask_reg[2];
815fe839d9SFabio Estevam
avic_irq_suspend(struct irq_data * d)823995eb82SShawn Guo static void avic_irq_suspend(struct irq_data *d)
833995eb82SShawn Guo {
843995eb82SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
853995eb82SShawn Guo struct irq_chip_type *ct = gc->chip_types;
863995eb82SShawn Guo int idx = d->hwirq >> 5;
873995eb82SShawn Guo
88c553138fSJohannes Berg avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
89c553138fSJohannes Berg imx_writel(gc->wake_active, avic_base + ct->regs.mask);
909b454d16SMartin Kaiser
919b454d16SMartin Kaiser if (mx25_ccm_base) {
929b454d16SMartin Kaiser u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
939b454d16SMartin Kaiser MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
949b454d16SMartin Kaiser /*
959b454d16SMartin Kaiser * The interrupts which are still enabled will be used as wakeup
969b454d16SMartin Kaiser * sources. Allow those interrupts in low-power mode.
979b454d16SMartin Kaiser * The LPIMR registers use 0 to allow an interrupt, the AVIC
989b454d16SMartin Kaiser * registers use 1.
999b454d16SMartin Kaiser */
1009b454d16SMartin Kaiser imx_writel(~gc->wake_active, mx25_ccm_base + offs);
1019b454d16SMartin Kaiser }
1023995eb82SShawn Guo }
1033995eb82SShawn Guo
avic_irq_resume(struct irq_data * d)1043995eb82SShawn Guo static void avic_irq_resume(struct irq_data *d)
1053995eb82SShawn Guo {
1063995eb82SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1073995eb82SShawn Guo struct irq_chip_type *ct = gc->chip_types;
1083995eb82SShawn Guo int idx = d->hwirq >> 5;
1093995eb82SShawn Guo
110c553138fSJohannes Berg imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
1119b454d16SMartin Kaiser
1129b454d16SMartin Kaiser if (mx25_ccm_base) {
1139b454d16SMartin Kaiser u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
1149b454d16SMartin Kaiser MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
1159b454d16SMartin Kaiser
1169b454d16SMartin Kaiser imx_writel(0xffffffff, mx25_ccm_base + offs);
1179b454d16SMartin Kaiser }
1183995eb82SShawn Guo }
1193995eb82SShawn Guo
1203995eb82SShawn Guo #else
1213995eb82SShawn Guo #define avic_irq_suspend NULL
1223995eb82SShawn Guo #define avic_irq_resume NULL
1233995eb82SShawn Guo #endif
1243995eb82SShawn Guo
avic_init_gc(int idx,unsigned int irq_start)1253995eb82SShawn Guo static __init void avic_init_gc(int idx, unsigned int irq_start)
1263995eb82SShawn Guo {
1273995eb82SShawn Guo struct irq_chip_generic *gc;
1283995eb82SShawn Guo struct irq_chip_type *ct;
1293995eb82SShawn Guo
1303995eb82SShawn Guo gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
1313995eb82SShawn Guo handle_level_irq);
1323995eb82SShawn Guo gc->private = &avic_extra_irq;
1333995eb82SShawn Guo gc->wake_enabled = IRQ_MSK(32);
1343995eb82SShawn Guo
1353995eb82SShawn Guo ct = gc->chip_types;
1363995eb82SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit;
1373995eb82SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit;
1383995eb82SShawn Guo ct->chip.irq_ack = irq_gc_mask_clr_bit;
1393995eb82SShawn Guo ct->chip.irq_set_wake = irq_gc_set_wake;
1403995eb82SShawn Guo ct->chip.irq_suspend = avic_irq_suspend;
1413995eb82SShawn Guo ct->chip.irq_resume = avic_irq_resume;
1423995eb82SShawn Guo ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
1433995eb82SShawn Guo ct->regs.ack = ct->regs.mask;
1443995eb82SShawn Guo
1453995eb82SShawn Guo irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
1463995eb82SShawn Guo }
1473995eb82SShawn Guo
avic_handle_irq(struct pt_regs * regs)148000bf9eeSAlexander Shiyan static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
1493995eb82SShawn Guo {
1503995eb82SShawn Guo u32 nivector;
1513995eb82SShawn Guo
1523995eb82SShawn Guo do {
153c553138fSJohannes Berg nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
1543995eb82SShawn Guo if (nivector == 0xffff)
1553995eb82SShawn Guo break;
1563995eb82SShawn Guo
157*0953fb26SMark Rutland generic_handle_domain_irq(domain, nivector);
1583995eb82SShawn Guo } while (1);
1593995eb82SShawn Guo }
1603995eb82SShawn Guo
1613995eb82SShawn Guo /*
1623995eb82SShawn Guo * This function initializes the AVIC hardware and disables all the
1633995eb82SShawn Guo * interrupts. It registers the interrupt enable and disable functions
1643995eb82SShawn Guo * to the kernel for each interrupt source.
1653995eb82SShawn Guo */
mxc_init_irq(void __iomem * irqbase)166e2c1b0ffSSaravana Kannan static void __init mxc_init_irq(void __iomem *irqbase)
1673995eb82SShawn Guo {
1683995eb82SShawn Guo struct device_node *np;
1693995eb82SShawn Guo int irq_base;
1703995eb82SShawn Guo int i;
1713995eb82SShawn Guo
1723995eb82SShawn Guo avic_base = irqbase;
1733995eb82SShawn Guo
1749b454d16SMartin Kaiser np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
1759b454d16SMartin Kaiser mx25_ccm_base = of_iomap(np, 0);
1769b454d16SMartin Kaiser
1779b454d16SMartin Kaiser if (mx25_ccm_base) {
1789b454d16SMartin Kaiser /*
1799b454d16SMartin Kaiser * By default, we mask all interrupts. We set the actual mask
1809b454d16SMartin Kaiser * before we go into low-power mode.
1819b454d16SMartin Kaiser */
1829b454d16SMartin Kaiser imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
1839b454d16SMartin Kaiser imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
1849b454d16SMartin Kaiser }
1859b454d16SMartin Kaiser
1863995eb82SShawn Guo /* put the AVIC into the reset value with
1873995eb82SShawn Guo * all interrupts disabled
1883995eb82SShawn Guo */
189c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_INTCNTL);
190c553138fSJohannes Berg imx_writel(0x1f, avic_base + AVIC_NIMASK);
1913995eb82SShawn Guo
1923995eb82SShawn Guo /* disable all interrupts */
193c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_INTENABLEH);
194c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_INTENABLEL);
1953995eb82SShawn Guo
1963995eb82SShawn Guo /* all IRQ no FIQ */
197c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_INTTYPEH);
198c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_INTTYPEL);
1993995eb82SShawn Guo
2003995eb82SShawn Guo irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
2013995eb82SShawn Guo WARN_ON(irq_base < 0);
2023995eb82SShawn Guo
2033995eb82SShawn Guo np = of_find_compatible_node(NULL, NULL, "fsl,avic");
2043995eb82SShawn Guo domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
2053995eb82SShawn Guo &irq_domain_simple_ops, NULL);
2063995eb82SShawn Guo WARN_ON(!domain);
2073995eb82SShawn Guo
2083995eb82SShawn Guo for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
2093995eb82SShawn Guo avic_init_gc(i, irq_base);
2103995eb82SShawn Guo
2113995eb82SShawn Guo /* Set default priority value (0) for all IRQ's */
2123995eb82SShawn Guo for (i = 0; i < 8; i++)
213c553138fSJohannes Berg imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
2143995eb82SShawn Guo
215000bf9eeSAlexander Shiyan set_handle_irq(avic_handle_irq);
216000bf9eeSAlexander Shiyan
2173995eb82SShawn Guo #ifdef CONFIG_FIQ
2183995eb82SShawn Guo /* Initialize FIQ */
2193995eb82SShawn Guo init_FIQ(FIQ_START);
2203995eb82SShawn Guo #endif
2213995eb82SShawn Guo
2223995eb82SShawn Guo printk(KERN_INFO "MXC IRQ initialized\n");
2233995eb82SShawn Guo }
224e2c1b0ffSSaravana Kannan
imx_avic_init(struct device_node * node,struct device_node * parent)225e2c1b0ffSSaravana Kannan static int __init imx_avic_init(struct device_node *node,
226e2c1b0ffSSaravana Kannan struct device_node *parent)
227e2c1b0ffSSaravana Kannan {
228e2c1b0ffSSaravana Kannan void __iomem *avic_base;
229e2c1b0ffSSaravana Kannan
230e2c1b0ffSSaravana Kannan avic_base = of_iomap(node, 0);
231e2c1b0ffSSaravana Kannan BUG_ON(!avic_base);
232e2c1b0ffSSaravana Kannan mxc_init_irq(avic_base);
233e2c1b0ffSSaravana Kannan return 0;
234e2c1b0ffSSaravana Kannan }
235e2c1b0ffSSaravana Kannan
236e2c1b0ffSSaravana Kannan IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init);
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