1 /* 2 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. 3 * Copyright 2017-2018 NXP. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/regmap.h> 19 #include "common.h" 20 #include "hardware.h" 21 22 #define REG_SET 0x4 23 #define REG_CLR 0x8 24 25 #define ANADIG_REG_2P5 0x130 26 #define ANADIG_REG_CORE 0x140 27 #define ANADIG_ANA_MISC0 0x150 28 #define ANADIG_USB1_CHRG_DETECT 0x1b0 29 #define ANADIG_USB2_CHRG_DETECT 0x210 30 #define ANADIG_DIGPROG 0x260 31 #define ANADIG_DIGPROG_IMX6SL 0x280 32 #define ANADIG_DIGPROG_IMX7D 0x800 33 34 #define SRC_SBMR2 0x1c 35 36 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 37 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 38 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 39 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 40 /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ 41 #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 42 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 43 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 44 45 static struct regmap *anatop; 46 47 static void imx_anatop_enable_weak2p5(bool enable) 48 { 49 u32 reg, val; 50 51 regmap_read(anatop, ANADIG_ANA_MISC0, &val); 52 53 /* can only be enabled when stop_mode_config is clear. */ 54 reg = ANADIG_REG_2P5; 55 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? 56 REG_SET : REG_CLR; 57 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); 58 } 59 60 static void imx_anatop_enable_fet_odrive(bool enable) 61 { 62 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), 63 BM_ANADIG_REG_CORE_FET_ODRIVE); 64 } 65 66 static inline void imx_anatop_enable_2p5_pulldown(bool enable) 67 { 68 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), 69 BM_ANADIG_REG_2P5_ENABLE_PULLDOWN); 70 } 71 72 static inline void imx_anatop_disconnect_high_snvs(bool enable) 73 { 74 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), 75 BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); 76 } 77 78 void imx_anatop_pre_suspend(void) 79 { 80 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) 81 imx_anatop_enable_2p5_pulldown(true); 82 else 83 imx_anatop_enable_weak2p5(true); 84 85 imx_anatop_enable_fet_odrive(true); 86 87 if (cpu_is_imx6sl()) 88 imx_anatop_disconnect_high_snvs(true); 89 } 90 91 void imx_anatop_post_resume(void) 92 { 93 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) 94 imx_anatop_enable_2p5_pulldown(false); 95 else 96 imx_anatop_enable_weak2p5(false); 97 98 imx_anatop_enable_fet_odrive(false); 99 100 if (cpu_is_imx6sl()) 101 imx_anatop_disconnect_high_snvs(false); 102 103 } 104 105 static void imx_anatop_usb_chrg_detect_disable(void) 106 { 107 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, 108 BM_ANADIG_USB_CHRG_DETECT_EN_B 109 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); 110 regmap_write(anatop, ANADIG_USB2_CHRG_DETECT, 111 BM_ANADIG_USB_CHRG_DETECT_EN_B | 112 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); 113 } 114 115 void __init imx_init_revision_from_anatop(void) 116 { 117 struct device_node *np; 118 void __iomem *anatop_base; 119 unsigned int revision; 120 u32 digprog; 121 u16 offset = ANADIG_DIGPROG; 122 u8 major_part, minor_part; 123 124 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 125 anatop_base = of_iomap(np, 0); 126 WARN_ON(!anatop_base); 127 if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) 128 offset = ANADIG_DIGPROG_IMX6SL; 129 if (of_device_is_compatible(np, "fsl,imx7d-anatop")) 130 offset = ANADIG_DIGPROG_IMX7D; 131 digprog = readl_relaxed(anatop_base + offset); 132 iounmap(anatop_base); 133 134 /* 135 * On i.MX7D digprog value match linux version format, so 136 * it needn't map again and we can use register value directly. 137 */ 138 if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { 139 revision = digprog & 0xff; 140 } else { 141 /* 142 * MAJOR: [15:8], the major silicon revison; 143 * MINOR: [7: 0], the minor silicon revison; 144 * 145 * please refer to the i.MX RM for the detailed 146 * silicon revison bit define. 147 * format the major part and minor part to match the 148 * linux kernel soc version format. 149 */ 150 major_part = (digprog >> 8) & 0xf; 151 minor_part = digprog & 0xf; 152 revision = ((major_part + 1) << 4) | minor_part; 153 154 if ((digprog >> 16) == MXC_CPU_IMX6ULL) { 155 void __iomem *src_base; 156 u32 sbmr2; 157 158 np = of_find_compatible_node(NULL, NULL, 159 "fsl,imx6ul-src"); 160 src_base = of_iomap(np, 0); 161 WARN_ON(!src_base); 162 sbmr2 = readl_relaxed(src_base + SRC_SBMR2); 163 iounmap(src_base); 164 165 /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */ 166 if (sbmr2 & (1 << 6)) { 167 digprog &= ~(0xff << 16); 168 digprog |= (MXC_CPU_IMX6ULZ << 16); 169 } 170 } 171 } 172 173 mxc_set_cpu_type(digprog >> 16 & 0xff); 174 imx_set_soc_revision(revision); 175 } 176 177 void __init imx_anatop_init(void) 178 { 179 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); 180 if (IS_ERR(anatop)) { 181 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); 182 return; 183 } 184 185 imx_anatop_usb_chrg_detect_disable(); 186 } 187