1e95dddb3SAnson Huang /* 25739b919SAnson Huang * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. 3e95dddb3SAnson Huang * 4e95dddb3SAnson Huang * The code contained herein is licensed under the GNU General Public 5e95dddb3SAnson Huang * License. You may obtain a copy of the GNU General Public License 6e95dddb3SAnson Huang * Version 2 or later at the following locations: 7e95dddb3SAnson Huang * 8e95dddb3SAnson Huang * http://www.opensource.org/licenses/gpl-license.html 9e95dddb3SAnson Huang * http://www.gnu.org/copyleft/gpl.html 10e95dddb3SAnson Huang */ 11e95dddb3SAnson Huang 12e95dddb3SAnson Huang #include <linux/err.h> 13e95dddb3SAnson Huang #include <linux/io.h> 14e95dddb3SAnson Huang #include <linux/of.h> 15e95dddb3SAnson Huang #include <linux/of_address.h> 16e95dddb3SAnson Huang #include <linux/mfd/syscon.h> 17e95dddb3SAnson Huang #include <linux/regmap.h> 18fcc4f9fcSFabio Estevam #include "common.h" 19f1c6f314SShawn Guo #include "hardware.h" 20e95dddb3SAnson Huang 21e95dddb3SAnson Huang #define REG_SET 0x4 22e95dddb3SAnson Huang #define REG_CLR 0x8 23e95dddb3SAnson Huang 24263475d4SAnson Huang #define ANADIG_REG_2P5 0x130 25e95dddb3SAnson Huang #define ANADIG_REG_CORE 0x140 26263475d4SAnson Huang #define ANADIG_ANA_MISC0 0x150 27e95dddb3SAnson Huang #define ANADIG_USB1_CHRG_DETECT 0x1b0 28e95dddb3SAnson Huang #define ANADIG_USB2_CHRG_DETECT 0x210 29e95dddb3SAnson Huang #define ANADIG_DIGPROG 0x260 30d8ce823fSShawn Guo #define ANADIG_DIGPROG_IMX6SL 0x280 315739b919SAnson Huang #define ANADIG_DIGPROG_IMX7D 0x800 32e95dddb3SAnson Huang 33263475d4SAnson Huang #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 34bc4abc3eSAnson Huang #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 35e95dddb3SAnson Huang #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 36263475d4SAnson Huang #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 37bc4abc3eSAnson Huang /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ 38bc4abc3eSAnson Huang #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 39e95dddb3SAnson Huang #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 40e95dddb3SAnson Huang #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 41e95dddb3SAnson Huang 42e95dddb3SAnson Huang static struct regmap *anatop; 43e95dddb3SAnson Huang 44263475d4SAnson Huang static void imx_anatop_enable_weak2p5(bool enable) 45263475d4SAnson Huang { 46263475d4SAnson Huang u32 reg, val; 47263475d4SAnson Huang 48263475d4SAnson Huang regmap_read(anatop, ANADIG_ANA_MISC0, &val); 49263475d4SAnson Huang 50263475d4SAnson Huang /* can only be enabled when stop_mode_config is clear. */ 51263475d4SAnson Huang reg = ANADIG_REG_2P5; 52263475d4SAnson Huang reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? 53263475d4SAnson Huang REG_SET : REG_CLR; 54263475d4SAnson Huang regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); 55263475d4SAnson Huang } 56263475d4SAnson Huang 57e95dddb3SAnson Huang static void imx_anatop_enable_fet_odrive(bool enable) 58e95dddb3SAnson Huang { 59e95dddb3SAnson Huang regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), 60e95dddb3SAnson Huang BM_ANADIG_REG_CORE_FET_ODRIVE); 61e95dddb3SAnson Huang } 62e95dddb3SAnson Huang 63bc4abc3eSAnson Huang static inline void imx_anatop_enable_2p5_pulldown(bool enable) 64bc4abc3eSAnson Huang { 65bc4abc3eSAnson Huang regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), 66bc4abc3eSAnson Huang BM_ANADIG_REG_2P5_ENABLE_PULLDOWN); 67bc4abc3eSAnson Huang } 68bc4abc3eSAnson Huang 69bc4abc3eSAnson Huang static inline void imx_anatop_disconnect_high_snvs(bool enable) 70bc4abc3eSAnson Huang { 71bc4abc3eSAnson Huang regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), 72bc4abc3eSAnson Huang BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); 73bc4abc3eSAnson Huang } 74bc4abc3eSAnson Huang 75e95dddb3SAnson Huang void imx_anatop_pre_suspend(void) 76e95dddb3SAnson Huang { 77bc4abc3eSAnson Huang if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) 78bc4abc3eSAnson Huang imx_anatop_enable_2p5_pulldown(true); 79bc4abc3eSAnson Huang else 80263475d4SAnson Huang imx_anatop_enable_weak2p5(true); 81bc4abc3eSAnson Huang 82e95dddb3SAnson Huang imx_anatop_enable_fet_odrive(true); 83bc4abc3eSAnson Huang 84bc4abc3eSAnson Huang if (cpu_is_imx6sl()) 85bc4abc3eSAnson Huang imx_anatop_disconnect_high_snvs(true); 86e95dddb3SAnson Huang } 87e95dddb3SAnson Huang 88e95dddb3SAnson Huang void imx_anatop_post_resume(void) 89e95dddb3SAnson Huang { 90bc4abc3eSAnson Huang if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) 91bc4abc3eSAnson Huang imx_anatop_enable_2p5_pulldown(false); 92bc4abc3eSAnson Huang else 93263475d4SAnson Huang imx_anatop_enable_weak2p5(false); 94bc4abc3eSAnson Huang 95bc4abc3eSAnson Huang imx_anatop_enable_fet_odrive(false); 96bc4abc3eSAnson Huang 97bc4abc3eSAnson Huang if (cpu_is_imx6sl()) 98bc4abc3eSAnson Huang imx_anatop_disconnect_high_snvs(false); 99bc4abc3eSAnson Huang 100e95dddb3SAnson Huang } 101e95dddb3SAnson Huang 102ddcb9aa6SPeter Chen static void imx_anatop_usb_chrg_detect_disable(void) 103e95dddb3SAnson Huang { 104e95dddb3SAnson Huang regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, 105e95dddb3SAnson Huang BM_ANADIG_USB_CHRG_DETECT_EN_B 106e95dddb3SAnson Huang | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); 107e95dddb3SAnson Huang regmap_write(anatop, ANADIG_USB2_CHRG_DETECT, 108e95dddb3SAnson Huang BM_ANADIG_USB_CHRG_DETECT_EN_B | 109e95dddb3SAnson Huang BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); 110e95dddb3SAnson Huang } 111e95dddb3SAnson Huang 112f1c6f314SShawn Guo void __init imx_init_revision_from_anatop(void) 113e95dddb3SAnson Huang { 1147006ba24SShawn Guo struct device_node *np; 1157006ba24SShawn Guo void __iomem *anatop_base; 116f1c6f314SShawn Guo unsigned int revision; 117f1c6f314SShawn Guo u32 digprog; 118d8ce823fSShawn Guo u16 offset = ANADIG_DIGPROG; 1197006ba24SShawn Guo 1207006ba24SShawn Guo np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 1217006ba24SShawn Guo anatop_base = of_iomap(np, 0); 1227006ba24SShawn Guo WARN_ON(!anatop_base); 123d8ce823fSShawn Guo if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) 124d8ce823fSShawn Guo offset = ANADIG_DIGPROG_IMX6SL; 1255739b919SAnson Huang if (of_device_is_compatible(np, "fsl,imx7d-anatop")) 1265739b919SAnson Huang offset = ANADIG_DIGPROG_IMX7D; 127d8ce823fSShawn Guo digprog = readl_relaxed(anatop_base + offset); 128f1c6f314SShawn Guo iounmap(anatop_base); 1297006ba24SShawn Guo 130f1c6f314SShawn Guo switch (digprog & 0xff) { 131f1c6f314SShawn Guo case 0: 132f1c6f314SShawn Guo revision = IMX_CHIP_REVISION_1_0; 133f1c6f314SShawn Guo break; 134f1c6f314SShawn Guo case 1: 135f1c6f314SShawn Guo revision = IMX_CHIP_REVISION_1_1; 136f1c6f314SShawn Guo break; 137f1c6f314SShawn Guo case 2: 138f1c6f314SShawn Guo revision = IMX_CHIP_REVISION_1_2; 139f1c6f314SShawn Guo break; 140c896e938SJason Liu case 3: 141c896e938SJason Liu revision = IMX_CHIP_REVISION_1_3; 142c896e938SJason Liu break; 143c896e938SJason Liu case 4: 144c896e938SJason Liu revision = IMX_CHIP_REVISION_1_4; 145c896e938SJason Liu break; 146c896e938SJason Liu case 5: 147c896e938SJason Liu /* 148c896e938SJason Liu * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked 149c896e938SJason Liu * as 'D' in Part Number last character. 150c896e938SJason Liu */ 151c896e938SJason Liu revision = IMX_CHIP_REVISION_1_5; 152c896e938SJason Liu break; 153f1c6f314SShawn Guo default: 154f1c6f314SShawn Guo revision = IMX_CHIP_REVISION_UNKNOWN; 155f1c6f314SShawn Guo } 156f1c6f314SShawn Guo 157f1c6f314SShawn Guo mxc_set_cpu_type(digprog >> 16 & 0xff); 158f1c6f314SShawn Guo imx_set_soc_revision(revision); 159e95dddb3SAnson Huang } 160e95dddb3SAnson Huang 161e95dddb3SAnson Huang void __init imx_anatop_init(void) 162e95dddb3SAnson Huang { 163e95dddb3SAnson Huang anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); 164e95dddb3SAnson Huang if (IS_ERR(anatop)) { 165e95dddb3SAnson Huang pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); 166e95dddb3SAnson Huang return; 167e95dddb3SAnson Huang } 168ddcb9aa6SPeter Chen 169ddcb9aa6SPeter Chen imx_anatop_usb_chrg_detect_disable(); 170e95dddb3SAnson Huang } 171