1 /* 2 * Copyright (c) 2013 Linaro Ltd. 3 * Copyright (c) 2013 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 #include <linux/cpu.h> 11 #include <linux/delay.h> 12 #include <linux/io.h> 13 #include <linux/of_address.h> 14 #include <linux/of_platform.h> 15 #include <asm/cacheflush.h> 16 #include <asm/smp_plat.h> 17 #include "core.h" 18 19 /* Sysctrl registers in Hi3620 SoC */ 20 #define SCISOEN 0xc0 21 #define SCISODIS 0xc4 22 #define SCPERPWREN 0xd0 23 #define SCPERPWRDIS 0xd4 24 #define SCCPUCOREEN 0xf4 25 #define SCCPUCOREDIS 0xf8 26 #define SCPERCTRL0 0x200 27 #define SCCPURSTEN 0x410 28 #define SCCPURSTDIS 0x414 29 30 /* 31 * bit definition in SCISOEN/SCPERPWREN/... 32 * 33 * CPU2_ISO_CTRL (1 << 5) 34 * CPU3_ISO_CTRL (1 << 6) 35 * ... 36 */ 37 #define CPU2_ISO_CTRL (1 << 5) 38 39 /* 40 * bit definition in SCPERCTRL0 41 * 42 * CPU0_WFI_MASK_CFG (1 << 28) 43 * CPU1_WFI_MASK_CFG (1 << 29) 44 * ... 45 */ 46 #define CPU0_WFI_MASK_CFG (1 << 28) 47 48 /* 49 * bit definition in SCCPURSTEN/... 50 * 51 * CPU0_SRST_REQ_EN (1 << 0) 52 * CPU1_SRST_REQ_EN (1 << 1) 53 * ... 54 */ 55 #define CPU0_HPM_SRST_REQ_EN (1 << 22) 56 #define CPU0_DBG_SRST_REQ_EN (1 << 12) 57 #define CPU0_NEON_SRST_REQ_EN (1 << 4) 58 #define CPU0_SRST_REQ_EN (1 << 0) 59 60 #define HIX5HD2_PERI_CRG20 0x50 61 #define CRG20_CPU1_RESET (1 << 17) 62 63 #define HIX5HD2_PERI_PMC0 0x1000 64 #define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8) 65 #define PMC0_CPU1_PMC_ENABLE (1 << 7) 66 #define PMC0_CPU1_POWERDOWN (1 << 3) 67 68 enum { 69 HI3620_CTRL, 70 ERROR_CTRL, 71 }; 72 73 static void __iomem *ctrl_base; 74 static int id; 75 76 static void set_cpu_hi3620(int cpu, bool enable) 77 { 78 u32 val = 0; 79 80 if (enable) { 81 /* MTCMOS set */ 82 if ((cpu == 2) || (cpu == 3)) 83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), 84 ctrl_base + SCPERPWREN); 85 udelay(100); 86 87 /* Enable core */ 88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); 89 90 /* unreset */ 91 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN 92 | CPU0_SRST_REQ_EN; 93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); 94 /* reset */ 95 val |= CPU0_HPM_SRST_REQ_EN; 96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); 97 98 /* ISO disable */ 99 if ((cpu == 2) || (cpu == 3)) 100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), 101 ctrl_base + SCISODIS); 102 udelay(1); 103 104 /* WFI Mask */ 105 val = readl_relaxed(ctrl_base + SCPERCTRL0); 106 val &= ~(CPU0_WFI_MASK_CFG << cpu); 107 writel_relaxed(val, ctrl_base + SCPERCTRL0); 108 109 /* Unreset */ 110 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN 111 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN; 112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); 113 } else { 114 /* wfi mask */ 115 val = readl_relaxed(ctrl_base + SCPERCTRL0); 116 val |= (CPU0_WFI_MASK_CFG << cpu); 117 writel_relaxed(val, ctrl_base + SCPERCTRL0); 118 119 /* disable core*/ 120 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); 121 122 if ((cpu == 2) || (cpu == 3)) { 123 /* iso enable */ 124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), 125 ctrl_base + SCISOEN); 126 udelay(1); 127 } 128 129 /* reset */ 130 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN 131 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN; 132 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); 133 134 if ((cpu == 2) || (cpu == 3)) { 135 /* MTCMOS unset */ 136 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), 137 ctrl_base + SCPERPWRDIS); 138 udelay(100); 139 } 140 } 141 } 142 143 static int hi3xxx_hotplug_init(void) 144 { 145 struct device_node *node; 146 147 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); 148 if (node) { 149 ctrl_base = of_iomap(node, 0); 150 id = HI3620_CTRL; 151 return 0; 152 } 153 id = ERROR_CTRL; 154 return -ENOENT; 155 } 156 157 void hi3xxx_set_cpu(int cpu, bool enable) 158 { 159 if (!ctrl_base) { 160 if (hi3xxx_hotplug_init() < 0) 161 return; 162 } 163 164 if (id == HI3620_CTRL) 165 set_cpu_hi3620(cpu, enable); 166 } 167 168 static bool hix5hd2_hotplug_init(void) 169 { 170 struct device_node *np; 171 172 np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl"); 173 if (np) { 174 ctrl_base = of_iomap(np, 0); 175 return true; 176 } 177 return false; 178 } 179 180 void hix5hd2_set_cpu(int cpu, bool enable) 181 { 182 u32 val = 0; 183 184 if (!ctrl_base) 185 if (!hix5hd2_hotplug_init()) 186 BUG(); 187 188 if (enable) { 189 /* power on cpu1 */ 190 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); 191 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN); 192 val |= PMC0_CPU1_PMC_ENABLE; 193 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); 194 /* unreset */ 195 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); 196 val &= ~CRG20_CPU1_RESET; 197 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); 198 } else { 199 /* power down cpu1 */ 200 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); 201 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN; 202 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK; 203 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0); 204 205 /* reset */ 206 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); 207 val |= CRG20_CPU1_RESET; 208 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20); 209 } 210 } 211 212 static inline void cpu_enter_lowpower(void) 213 { 214 unsigned int v; 215 216 flush_cache_all(); 217 218 /* 219 * Turn off coherency and L1 D-cache 220 */ 221 asm volatile( 222 " mrc p15, 0, %0, c1, c0, 1\n" 223 " bic %0, %0, #0x40\n" 224 " mcr p15, 0, %0, c1, c0, 1\n" 225 " mrc p15, 0, %0, c1, c0, 0\n" 226 " bic %0, %0, #0x04\n" 227 " mcr p15, 0, %0, c1, c0, 0\n" 228 : "=&r" (v) 229 : "r" (0) 230 : "cc"); 231 } 232 233 #ifdef CONFIG_HOTPLUG_CPU 234 void hi3xxx_cpu_die(unsigned int cpu) 235 { 236 cpu_enter_lowpower(); 237 hi3xxx_set_cpu_jump(cpu, phys_to_virt(0)); 238 cpu_do_idle(); 239 240 /* We should have never returned from idle */ 241 panic("cpu %d unexpectedly exit from shutdown\n", cpu); 242 } 243 244 int hi3xxx_cpu_kill(unsigned int cpu) 245 { 246 unsigned long timeout = jiffies + msecs_to_jiffies(50); 247 248 while (hi3xxx_get_cpu_jump(cpu)) 249 if (time_after(jiffies, timeout)) 250 return 0; 251 hi3xxx_set_cpu(cpu, false); 252 return 1; 253 } 254 255 void hix5hd2_cpu_die(unsigned int cpu) 256 { 257 flush_cache_all(); 258 hix5hd2_set_cpu(cpu, false); 259 } 260 #endif 261