1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2011 Calxeda, Inc. 4 */ 5 #ifndef _MACH_HIGHBANK__SYSREGS_H_ 6 #define _MACH_HIGHBANK__SYSREGS_H_ 7 8 #include <linux/io.h> 9 #include <linux/smp.h> 10 #include <asm/smp_plat.h> 11 #include <asm/smp_scu.h> 12 #include "core.h" 13 14 extern void __iomem *sregs_base; 15 16 #define HB_SREG_A9_PWR_REQ 0xf00 17 #define HB_SREG_A9_BOOT_STAT 0xf04 18 #define HB_SREG_A9_BOOT_DATA 0xf08 19 20 #define HB_PWR_SUSPEND 0 21 #define HB_PWR_SOFT_RESET 1 22 #define HB_PWR_HARD_RESET 2 23 #define HB_PWR_SHUTDOWN 3 24 25 #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4)) 26 27 static inline void highbank_set_core_pwr(void) 28 { 29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); 30 if (scu_base_addr) 31 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); 32 else 33 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); 34 } 35 36 static inline void highbank_clear_core_pwr(void) 37 { 38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); 39 if (scu_base_addr) 40 scu_power_mode(scu_base_addr, SCU_PM_NORMAL); 41 else 42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); 43 } 44 45 static inline void highbank_set_pwr_suspend(void) 46 { 47 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); 48 highbank_set_core_pwr(); 49 } 50 51 static inline void highbank_set_pwr_shutdown(void) 52 { 53 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); 54 highbank_set_core_pwr(); 55 } 56 57 static inline void highbank_set_pwr_soft_reset(void) 58 { 59 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 60 highbank_set_core_pwr(); 61 } 62 63 static inline void highbank_set_pwr_hard_reset(void) 64 { 65 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 66 highbank_set_core_pwr(); 67 } 68 69 static inline void highbank_clear_pwr_request(void) 70 { 71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); 72 highbank_clear_core_pwr(); 73 } 74 75 #endif 76