1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a09e64fbSRussell King /* 3a09e64fbSRussell King * arch/arm/mach-footbridge/include/mach/hardware.h 4a09e64fbSRussell King * 5a09e64fbSRussell King * Copyright (C) 1998-1999 Russell King. 6a09e64fbSRussell King * 7a09e64fbSRussell King * This file contains the hardware definitions of the EBSA-285. 8a09e64fbSRussell King */ 9a09e64fbSRussell King #ifndef __ASM_ARCH_HARDWARE_H 10a09e64fbSRussell King #define __ASM_ARCH_HARDWARE_H 11a09e64fbSRussell King 12a09e64fbSRussell King /* Virtual Physical Size 13a09e64fbSRussell King * 0xff800000 0x40000000 1MB X-Bus 14a09e64fbSRussell King * 0xff000000 0x7c000000 1MB PCI I/O space 15a09e64fbSRussell King * 0xfe000000 0x42000000 1MB CSR 16a09e64fbSRussell King * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 17a09e64fbSRussell King * 0xfc000000 0x79000000 1MB PCI IACK/special space 18a09e64fbSRussell King * 0xfb000000 0x7a000000 16MB PCI Config type 1 19a09e64fbSRussell King * 0xfa000000 0x7b000000 16MB PCI Config type 0 20a09e64fbSRussell King * 0xf9000000 0x50000000 1MB Cache flush 21a09e64fbSRussell King * 0xf0000000 0x80000000 16MB ISA memory 22a09e64fbSRussell King */ 236fa85e5cSStepan Moskovchenko 246fa85e5cSStepan Moskovchenko #ifdef CONFIG_MMU 256fa85e5cSStepan Moskovchenko #define MMU_IO(a, b) (a) 266fa85e5cSStepan Moskovchenko #else 276fa85e5cSStepan Moskovchenko #define MMU_IO(a, b) (b) 286fa85e5cSStepan Moskovchenko #endif 296fa85e5cSStepan Moskovchenko 30a09e64fbSRussell King #define XBUS_SIZE 0x00100000 316fa85e5cSStepan Moskovchenko #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) 32a09e64fbSRussell King 33a09e64fbSRussell King #define ARMCSR_SIZE 0x00100000 346fa85e5cSStepan Moskovchenko #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) 35a09e64fbSRussell King 36a09e64fbSRussell King #define WFLUSH_SIZE 0x00100000 376fa85e5cSStepan Moskovchenko #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) 38a09e64fbSRussell King 39a09e64fbSRussell King #define PCIIACK_SIZE 0x00100000 406fa85e5cSStepan Moskovchenko #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) 41a09e64fbSRussell King 42a09e64fbSRussell King #define PCICFG1_SIZE 0x01000000 436fa85e5cSStepan Moskovchenko #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) 44a09e64fbSRussell King 45a09e64fbSRussell King #define PCICFG0_SIZE 0x01000000 466fa85e5cSStepan Moskovchenko #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) 47a09e64fbSRussell King 48a09e64fbSRussell King #define PCIMEM_SIZE 0x01000000 496fa85e5cSStepan Moskovchenko #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) 50a09e64fbSRussell King 5143024ed6SRussell King #define XBUS_CS2 0x40012000 52a09e64fbSRussell King 53a09e64fbSRussell King #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 54a09e64fbSRussell King #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 55a09e64fbSRussell King #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 56a09e64fbSRussell King #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 57a09e64fbSRussell King #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 58a09e64fbSRussell King 59c94e4ad2SRussell King #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ 60a09e64fbSRussell King 61a09e64fbSRussell King 62a09e64fbSRussell King /* PIC irq control */ 63a09e64fbSRussell King #define PIC_LO 0x20 64a09e64fbSRussell King #define PIC_MASK_LO 0x21 65a09e64fbSRussell King #define PIC_HI 0xA0 66a09e64fbSRussell King #define PIC_MASK_HI 0xA1 67a09e64fbSRussell King 68a09e64fbSRussell King /* GPIO pins */ 69a09e64fbSRussell King #define GPIO_CCLK 0x800 70a09e64fbSRussell King #define GPIO_DSCLK 0x400 71a09e64fbSRussell King #define GPIO_E2CLK 0x200 72a09e64fbSRussell King #define GPIO_IOLOAD 0x100 73a09e64fbSRussell King #define GPIO_RED_LED 0x080 74a09e64fbSRussell King #define GPIO_WDTIMER 0x040 75a09e64fbSRussell King #define GPIO_DATA 0x020 76a09e64fbSRussell King #define GPIO_IOCLK 0x010 77a09e64fbSRussell King #define GPIO_DONE 0x008 78a09e64fbSRussell King #define GPIO_FAN 0x004 79a09e64fbSRussell King #define GPIO_GREEN_LED 0x002 80a09e64fbSRussell King #define GPIO_RESET 0x001 81a09e64fbSRussell King 82a09e64fbSRussell King /* CPLD pins */ 83a09e64fbSRussell King #define CPLD_DS_ENABLE 8 84a09e64fbSRussell King #define CPLD_7111_DISABLE 4 85a09e64fbSRussell King #define CPLD_UNMUTE 2 86a09e64fbSRussell King #define CPLD_FLASH_WR_ENABLE 1 87a09e64fbSRussell King 88a09e64fbSRussell King #ifndef __ASSEMBLY__ 89bd31b859SThomas Gleixner extern raw_spinlock_t nw_gpio_lock; 9070d13e08SRussell King extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 9170d13e08SRussell King extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 9270d13e08SRussell King extern unsigned int nw_gpio_read(void); 9370d13e08SRussell King extern void nw_cpld_modify(unsigned int mask, unsigned int set); 94a09e64fbSRussell King #endif 95a09e64fbSRussell King 96a09e64fbSRussell King #endif 97