1a09e64fbSRussell King /* 2a09e64fbSRussell King * arch/arm/mach-footbridge/include/mach/hardware.h 3a09e64fbSRussell King * 4a09e64fbSRussell King * Copyright (C) 1998-1999 Russell King. 5a09e64fbSRussell King * 6a09e64fbSRussell King * This program is free software; you can redistribute it and/or modify 7a09e64fbSRussell King * it under the terms of the GNU General Public License version 2 as 8a09e64fbSRussell King * published by the Free Software Foundation. 9a09e64fbSRussell King * 10a09e64fbSRussell King * This file contains the hardware definitions of the EBSA-285. 11a09e64fbSRussell King */ 12a09e64fbSRussell King #ifndef __ASM_ARCH_HARDWARE_H 13a09e64fbSRussell King #define __ASM_ARCH_HARDWARE_H 14a09e64fbSRussell King 15a09e64fbSRussell King /* Virtual Physical Size 16a09e64fbSRussell King * 0xff800000 0x40000000 1MB X-Bus 17a09e64fbSRussell King * 0xff000000 0x7c000000 1MB PCI I/O space 18a09e64fbSRussell King * 0xfe000000 0x42000000 1MB CSR 19a09e64fbSRussell King * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 20a09e64fbSRussell King * 0xfc000000 0x79000000 1MB PCI IACK/special space 21a09e64fbSRussell King * 0xfb000000 0x7a000000 16MB PCI Config type 1 22a09e64fbSRussell King * 0xfa000000 0x7b000000 16MB PCI Config type 0 23a09e64fbSRussell King * 0xf9000000 0x50000000 1MB Cache flush 24a09e64fbSRussell King * 0xf0000000 0x80000000 16MB ISA memory 25a09e64fbSRussell King */ 266fa85e5cSStepan Moskovchenko 276fa85e5cSStepan Moskovchenko #ifdef CONFIG_MMU 286fa85e5cSStepan Moskovchenko #define MMU_IO(a, b) (a) 296fa85e5cSStepan Moskovchenko #else 306fa85e5cSStepan Moskovchenko #define MMU_IO(a, b) (b) 316fa85e5cSStepan Moskovchenko #endif 326fa85e5cSStepan Moskovchenko 33a09e64fbSRussell King #define XBUS_SIZE 0x00100000 346fa85e5cSStepan Moskovchenko #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) 35a09e64fbSRussell King 36a09e64fbSRussell King #define ARMCSR_SIZE 0x00100000 376fa85e5cSStepan Moskovchenko #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) 38a09e64fbSRussell King 39a09e64fbSRussell King #define WFLUSH_SIZE 0x00100000 406fa85e5cSStepan Moskovchenko #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) 41a09e64fbSRussell King 42a09e64fbSRussell King #define PCIIACK_SIZE 0x00100000 436fa85e5cSStepan Moskovchenko #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) 44a09e64fbSRussell King 45a09e64fbSRussell King #define PCICFG1_SIZE 0x01000000 466fa85e5cSStepan Moskovchenko #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) 47a09e64fbSRussell King 48a09e64fbSRussell King #define PCICFG0_SIZE 0x01000000 496fa85e5cSStepan Moskovchenko #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) 50a09e64fbSRussell King 51a09e64fbSRussell King #define PCIMEM_SIZE 0x01000000 526fa85e5cSStepan Moskovchenko #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) 53a09e64fbSRussell King 5443024ed6SRussell King #define XBUS_CS2 0x40012000 55a09e64fbSRussell King 56a09e64fbSRussell King #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 57a09e64fbSRussell King #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 58a09e64fbSRussell King #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 59a09e64fbSRussell King #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 60a09e64fbSRussell King #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 61a09e64fbSRussell King 62c94e4ad2SRussell King #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ 63a09e64fbSRussell King 64a09e64fbSRussell King 65a09e64fbSRussell King /* PIC irq control */ 66a09e64fbSRussell King #define PIC_LO 0x20 67a09e64fbSRussell King #define PIC_MASK_LO 0x21 68a09e64fbSRussell King #define PIC_HI 0xA0 69a09e64fbSRussell King #define PIC_MASK_HI 0xA1 70a09e64fbSRussell King 71a09e64fbSRussell King /* GPIO pins */ 72a09e64fbSRussell King #define GPIO_CCLK 0x800 73a09e64fbSRussell King #define GPIO_DSCLK 0x400 74a09e64fbSRussell King #define GPIO_E2CLK 0x200 75a09e64fbSRussell King #define GPIO_IOLOAD 0x100 76a09e64fbSRussell King #define GPIO_RED_LED 0x080 77a09e64fbSRussell King #define GPIO_WDTIMER 0x040 78a09e64fbSRussell King #define GPIO_DATA 0x020 79a09e64fbSRussell King #define GPIO_IOCLK 0x010 80a09e64fbSRussell King #define GPIO_DONE 0x008 81a09e64fbSRussell King #define GPIO_FAN 0x004 82a09e64fbSRussell King #define GPIO_GREEN_LED 0x002 83a09e64fbSRussell King #define GPIO_RESET 0x001 84a09e64fbSRussell King 85a09e64fbSRussell King /* CPLD pins */ 86a09e64fbSRussell King #define CPLD_DS_ENABLE 8 87a09e64fbSRussell King #define CPLD_7111_DISABLE 4 88a09e64fbSRussell King #define CPLD_UNMUTE 2 89a09e64fbSRussell King #define CPLD_FLASH_WR_ENABLE 1 90a09e64fbSRussell King 91a09e64fbSRussell King #ifndef __ASSEMBLY__ 92bd31b859SThomas Gleixner extern raw_spinlock_t nw_gpio_lock; 9370d13e08SRussell King extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 9470d13e08SRussell King extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 9570d13e08SRussell King extern unsigned int nw_gpio_read(void); 9670d13e08SRussell King extern void nw_cpld_modify(unsigned int mask, unsigned int set); 97a09e64fbSRussell King #endif 98a09e64fbSRussell King 99a09e64fbSRussell King #endif 100