1 /* 2 * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285 3 * 4 * Copyright (C) 1998-2001 Russell King 5 * Copyright (C) 1998-2000 Phil Blundell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/pci.h> 13 #include <linux/interrupt.h> 14 #include <linux/mm.h> 15 #include <linux/slab.h> 16 #include <linux/init.h> 17 #include <linux/ioport.h> 18 #include <linux/irq.h> 19 #include <linux/io.h> 20 #include <linux/spinlock.h> 21 22 #include <asm/irq.h> 23 #include <asm/mach/pci.h> 24 #include <asm/hardware/dec21285.h> 25 26 #define MAX_SLOTS 21 27 28 #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \ 29 PCI_STATUS_REC_TARGET_ABORT)<<16) 30 31 #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \ 32 PCI_STATUS_REC_MASTER_ABORT | \ 33 PCI_STATUS_REC_TARGET_ABORT | \ 34 PCI_STATUS_PARITY) << 16) 35 36 extern int setup_arm_irq(int, struct irqaction *); 37 extern void pcibios_report_status(u_int status_mask, int warn); 38 39 static unsigned long 40 dc21285_base_address(struct pci_bus *bus, unsigned int devfn) 41 { 42 unsigned long addr = 0; 43 44 if (bus->number == 0) { 45 if (PCI_SLOT(devfn) == 0) 46 /* 47 * For devfn 0, point at the 21285 48 */ 49 addr = ARMCSR_BASE; 50 else { 51 devfn -= 1 << 3; 52 53 if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) 54 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8); 55 } 56 } else 57 addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8); 58 59 return addr; 60 } 61 62 static int 63 dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where, 64 int size, u32 *value) 65 { 66 unsigned long addr = dc21285_base_address(bus, devfn); 67 u32 v = 0xffffffff; 68 69 if (addr) 70 switch (size) { 71 case 1: 72 asm("ldrb %0, [%1, %2]" 73 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 74 break; 75 case 2: 76 asm("ldrh %0, [%1, %2]" 77 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 78 break; 79 case 4: 80 asm("ldr %0, [%1, %2]" 81 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 82 break; 83 } 84 85 *value = v; 86 87 v = *CSR_PCICMD; 88 if (v & PCICMD_ABORT) { 89 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT); 90 return -1; 91 } 92 93 return PCIBIOS_SUCCESSFUL; 94 } 95 96 static int 97 dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where, 98 int size, u32 value) 99 { 100 unsigned long addr = dc21285_base_address(bus, devfn); 101 u32 v; 102 103 if (addr) 104 switch (size) { 105 case 1: 106 asm("strb %0, [%1, %2]" 107 : : "r" (value), "r" (addr), "r" (where) 108 : "cc"); 109 break; 110 case 2: 111 asm("strh %0, [%1, %2]" 112 : : "r" (value), "r" (addr), "r" (where) 113 : "cc"); 114 break; 115 case 4: 116 asm("str %0, [%1, %2]" 117 : : "r" (value), "r" (addr), "r" (where) 118 : "cc"); 119 break; 120 } 121 122 v = *CSR_PCICMD; 123 if (v & PCICMD_ABORT) { 124 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT); 125 return -1; 126 } 127 128 return PCIBIOS_SUCCESSFUL; 129 } 130 131 struct pci_ops dc21285_ops = { 132 .read = dc21285_read_config, 133 .write = dc21285_write_config, 134 }; 135 136 static struct timer_list serr_timer; 137 static struct timer_list perr_timer; 138 139 static void dc21285_enable_error(struct timer_list *timer) 140 { 141 del_timer(timer); 142 143 if (timer == &serr_timer) 144 enable_irq(IRQ_PCI_SERR); 145 else if (timer == &perr_timer) 146 enable_irq(IRQ_PCI_PERR); 147 } 148 149 /* 150 * Warn on PCI errors. 151 */ 152 static irqreturn_t dc21285_abort_irq(int irq, void *dev_id) 153 { 154 unsigned int cmd; 155 unsigned int status; 156 157 cmd = *CSR_PCICMD; 158 status = cmd >> 16; 159 cmd = cmd & 0xffff; 160 161 if (status & PCI_STATUS_REC_MASTER_ABORT) { 162 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", 163 instruction_pointer(get_irq_regs())); 164 cmd |= PCI_STATUS_REC_MASTER_ABORT << 16; 165 } 166 167 if (status & PCI_STATUS_REC_TARGET_ABORT) { 168 printk(KERN_DEBUG "PCI: target abort: "); 169 pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT | 170 PCI_STATUS_SIG_TARGET_ABORT | 171 PCI_STATUS_REC_TARGET_ABORT, 1); 172 printk("\n"); 173 174 cmd |= PCI_STATUS_REC_TARGET_ABORT << 16; 175 } 176 177 *CSR_PCICMD = cmd; 178 179 return IRQ_HANDLED; 180 } 181 182 static irqreturn_t dc21285_serr_irq(int irq, void *dev_id) 183 { 184 struct timer_list *timer = dev_id; 185 unsigned int cntl; 186 187 printk(KERN_DEBUG "PCI: system error received: "); 188 pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1); 189 printk("\n"); 190 191 cntl = *CSR_SA110_CNTL & 0xffffdf07; 192 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; 193 194 /* 195 * back off this interrupt 196 */ 197 disable_irq(irq); 198 timer->expires = jiffies + HZ; 199 add_timer(timer); 200 201 return IRQ_HANDLED; 202 } 203 204 static irqreturn_t dc21285_discard_irq(int irq, void *dev_id) 205 { 206 printk(KERN_DEBUG "PCI: discard timer expired\n"); 207 *CSR_SA110_CNTL &= 0xffffde07; 208 209 return IRQ_HANDLED; 210 } 211 212 static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id) 213 { 214 unsigned int cmd; 215 216 printk(KERN_DEBUG "PCI: data parity error detected: "); 217 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1); 218 printk("\n"); 219 220 cmd = *CSR_PCICMD & 0xffff; 221 *CSR_PCICMD = cmd | 1 << 24; 222 223 return IRQ_HANDLED; 224 } 225 226 static irqreturn_t dc21285_parity_irq(int irq, void *dev_id) 227 { 228 struct timer_list *timer = dev_id; 229 unsigned int cmd; 230 231 printk(KERN_DEBUG "PCI: parity error detected: "); 232 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1); 233 printk("\n"); 234 235 cmd = *CSR_PCICMD & 0xffff; 236 *CSR_PCICMD = cmd | 1 << 31; 237 238 /* 239 * back off this interrupt 240 */ 241 disable_irq(irq); 242 timer->expires = jiffies + HZ; 243 add_timer(timer); 244 245 return IRQ_HANDLED; 246 } 247 248 int __init dc21285_setup(int nr, struct pci_sys_data *sys) 249 { 250 struct resource *res; 251 252 if (nr || !footbridge_cfn_mode()) 253 return 0; 254 255 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 256 if (!res) { 257 printk("out of memory for root bus resources"); 258 return 0; 259 } 260 261 res[0].flags = IORESOURCE_MEM; 262 res[0].name = "Footbridge non-prefetch"; 263 res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 264 res[1].name = "Footbridge prefetch"; 265 266 allocate_resource(&iomem_resource, &res[1], 0x20000000, 267 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL); 268 allocate_resource(&iomem_resource, &res[0], 0x40000000, 269 0x80000000, 0xffffffff, 0x40000000, NULL, NULL); 270 271 sys->mem_offset = DC21285_PCI_MEM; 272 273 pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); 274 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 275 276 return 1; 277 } 278 279 #define dc21285_request_irq(_a, _b, _c, _d, _e) \ 280 WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0) 281 282 void __init dc21285_preinit(void) 283 { 284 unsigned int mem_size, mem_mask; 285 int cfn_mode; 286 287 pcibios_min_mem = 0x81000000; 288 289 mem_size = (unsigned int)high_memory - PAGE_OFFSET; 290 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) 291 if (mem_mask >= mem_size) 292 break; 293 294 /* 295 * These registers need to be set up whether we're the 296 * central function or not. 297 */ 298 *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000; 299 *CSR_SDRAMBASEOFFSET = 0; 300 *CSR_ROMBASEMASK = 0x80000000; 301 *CSR_CSRBASEMASK = 0; 302 *CSR_CSRBASEOFFSET = 0; 303 *CSR_PCIADDR_EXTN = 0; 304 305 cfn_mode = __footbridge_cfn_mode(); 306 307 printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in " 308 "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ? 309 "central function" : "addin"); 310 311 if (footbridge_cfn_mode()) { 312 /* 313 * Clear any existing errors - we aren't 314 * interested in historical data... 315 */ 316 *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | 317 SA110_CNTL_RXSERR; 318 *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS; 319 } 320 321 timer_setup(&serr_timer, dc21285_enable_error, 0); 322 timer_setup(&perr_timer, dc21285_enable_error, 0); 323 324 /* 325 * We don't care if these fail. 326 */ 327 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0, 328 "PCI system error", &serr_timer); 329 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0, 330 "PCI parity error", &perr_timer); 331 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0, 332 "PCI abort", NULL); 333 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0, 334 "Discard timer", NULL); 335 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0, 336 "PCI data parity", NULL); 337 338 if (cfn_mode) { 339 /* 340 * Map our SDRAM at a known address in PCI space, just in case 341 * the firmware had other ideas. Using a nonzero base is 342 * necessary, since some VGA cards forcefully use PCI addresses 343 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). 344 */ 345 *CSR_PCICSRBASE = 0xf4000000; 346 *CSR_PCICSRIOBASE = 0; 347 *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); 348 *CSR_PCIROMBASE = 0; 349 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 350 PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS; 351 } else if (footbridge_cfn_mode() != 0) { 352 /* 353 * If we are not compiled to accept "add-in" mode, then 354 * we are using a constant virt_to_bus translation which 355 * can not hope to cater for the way the host BIOS has 356 * set up the machine. 357 */ 358 panic("PCI: this kernel is compiled for central " 359 "function mode only"); 360 } 361 } 362 363 void __init dc21285_postinit(void) 364 { 365 register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0); 366 } 367