1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/arch/arm/mach-footbridge/common.c
4  *
5  *  Copyright (C) 1998-2000 Russell King, Dave Gilbert.
6  */
7 #include <linux/module.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/ioport.h>
11 #include <linux/list.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/spinlock.h>
15 #include <video/vga.h>
16 
17 #include <asm/page.h>
18 #include <asm/irq.h>
19 #include <asm/mach-types.h>
20 #include <asm/setup.h>
21 #include <asm/system_misc.h>
22 #include <asm/hardware/dec21285.h>
23 
24 #include <asm/mach/irq.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/pci.h>
27 
28 #include "common.h"
29 
30 unsigned int mem_fclk_21285 = 50000000;
31 
32 EXPORT_SYMBOL(mem_fclk_21285);
33 
34 static int __init early_fclk(char *arg)
35 {
36 	mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
37 	return 0;
38 }
39 
40 early_param("mem_fclk_21285", early_fclk);
41 
42 static int __init parse_tag_memclk(const struct tag *tag)
43 {
44 	mem_fclk_21285 = tag->u.memclk.fmemclk;
45 	return 0;
46 }
47 
48 __tagtable(ATAG_MEMCLK, parse_tag_memclk);
49 
50 /*
51  * Footbridge IRQ translation table
52  *  Converts from our IRQ numbers into FootBridge masks
53  */
54 static const int fb_irq_mask[] = {
55 	IRQ_MASK_UART_RX,	/*  0 */
56 	IRQ_MASK_UART_TX,	/*  1 */
57 	IRQ_MASK_TIMER1,	/*  2 */
58 	IRQ_MASK_TIMER2,	/*  3 */
59 	IRQ_MASK_TIMER3,	/*  4 */
60 	IRQ_MASK_IN0,		/*  5 */
61 	IRQ_MASK_IN1,		/*  6 */
62 	IRQ_MASK_IN2,		/*  7 */
63 	IRQ_MASK_IN3,		/*  8 */
64 	IRQ_MASK_DOORBELLHOST,	/*  9 */
65 	IRQ_MASK_DMA1,		/* 10 */
66 	IRQ_MASK_DMA2,		/* 11 */
67 	IRQ_MASK_PCI,		/* 12 */
68 	IRQ_MASK_SDRAMPARITY,	/* 13 */
69 	IRQ_MASK_I2OINPOST,	/* 14 */
70 	IRQ_MASK_PCI_ABORT,	/* 15 */
71 	IRQ_MASK_PCI_SERR,	/* 16 */
72 	IRQ_MASK_DISCARD_TIMER,	/* 17 */
73 	IRQ_MASK_PCI_DPERR,	/* 18 */
74 	IRQ_MASK_PCI_PERR,	/* 19 */
75 };
76 
77 static void fb_mask_irq(struct irq_data *d)
78 {
79 	*CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
80 }
81 
82 static void fb_unmask_irq(struct irq_data *d)
83 {
84 	*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
85 }
86 
87 static struct irq_chip fb_chip = {
88 	.irq_ack	= fb_mask_irq,
89 	.irq_mask	= fb_mask_irq,
90 	.irq_unmask	= fb_unmask_irq,
91 };
92 
93 static void __init __fb_init_irq(void)
94 {
95 	unsigned int irq;
96 
97 	/*
98 	 * setup DC21285 IRQs
99 	 */
100 	*CSR_IRQ_DISABLE = -1;
101 	*CSR_FIQ_DISABLE = -1;
102 
103 	for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
104 		irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
105 		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
106 	}
107 }
108 
109 void __init footbridge_init_irq(void)
110 {
111 	__fb_init_irq();
112 
113 	if (!footbridge_cfn_mode())
114 		return;
115 
116 	if (machine_is_ebsa285())
117 		/* The following is dependent on which slot
118 		 * you plug the Southbridge card into.  We
119 		 * currently assume that you plug it into
120 		 * the right-hand most slot.
121 		 */
122 		isa_init_irq(IRQ_PCI);
123 
124 	if (machine_is_cats())
125 		isa_init_irq(IRQ_IN2);
126 
127 	if (machine_is_netwinder())
128 		isa_init_irq(IRQ_IN3);
129 }
130 
131 /*
132  * Common mapping for all systems.  Note that the outbound write flush is
133  * commented out since there is a "No Fix" problem with it.  Not mapping
134  * it means that we have extra bullet protection on our feet.
135  */
136 static struct map_desc fb_common_io_desc[] __initdata = {
137 	{
138 		.virtual	= ARMCSR_BASE,
139 		.pfn		= __phys_to_pfn(DC21285_ARMCSR_BASE),
140 		.length		= ARMCSR_SIZE,
141 		.type		= MT_DEVICE,
142 	}
143 };
144 
145 /*
146  * The mapping when the footbridge is in host mode.  We don't map any of
147  * this when we are in add-in mode.
148  */
149 static struct map_desc ebsa285_host_io_desc[] __initdata = {
150 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
151 	{
152 		.virtual	= PCIMEM_BASE,
153 		.pfn		= __phys_to_pfn(DC21285_PCI_MEM),
154 		.length		= PCIMEM_SIZE,
155 		.type		= MT_DEVICE,
156 	}, {
157 		.virtual	= PCICFG0_BASE,
158 		.pfn		= __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
159 		.length		= PCICFG0_SIZE,
160 		.type		= MT_DEVICE,
161 	}, {
162 		.virtual	= PCICFG1_BASE,
163 		.pfn		= __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
164 		.length		= PCICFG1_SIZE,
165 		.type		= MT_DEVICE,
166 	}, {
167 		.virtual	= PCIIACK_BASE,
168 		.pfn		= __phys_to_pfn(DC21285_PCI_IACK),
169 		.length		= PCIIACK_SIZE,
170 		.type		= MT_DEVICE,
171 	},
172 #endif
173 };
174 
175 void __init footbridge_map_io(void)
176 {
177 	/*
178 	 * Set up the common mapping first; we need this to
179 	 * determine whether we're in host mode or not.
180 	 */
181 	iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
182 
183 	/*
184 	 * Now, work out what we've got to map in addition on this
185 	 * platform.
186 	 */
187 	if (footbridge_cfn_mode()) {
188 		iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
189 		pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
190 	}
191 
192 	vga_base = PCIMEM_BASE;
193 }
194 
195 void footbridge_restart(enum reboot_mode mode, const char *cmd)
196 {
197 	if (mode == REBOOT_SOFT) {
198 		/* Jump into the ROM */
199 		soft_restart(0x41000000);
200 	} else {
201 		/*
202 		 * Force the watchdog to do a CPU reset.
203 		 *
204 		 * After making sure that the watchdog is disabled
205 		 * (so we can change the timer registers) we first
206 		 * enable the timer to autoreload itself.  Next, the
207 		 * timer interval is set really short and any
208 		 * current interrupt request is cleared (so we can
209 		 * see an edge transition).  Finally, TIMER4 is
210 		 * enabled as the watchdog.
211 		 */
212 		*CSR_SA110_CNTL &= ~(1 << 13);
213 		*CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
214 				   TIMER_CNTL_AUTORELOAD |
215 				   TIMER_CNTL_DIV16;
216 		*CSR_TIMER4_LOAD = 0x2;
217 		*CSR_TIMER4_CLR  = 0;
218 		*CSR_SA110_CNTL |= (1 << 13);
219 	}
220 }
221 
222 #ifdef CONFIG_FOOTBRIDGE_ADDIN
223 
224 static inline unsigned long fb_bus_sdram_offset(void)
225 {
226 	return *CSR_PCISDRAMBASE & 0xfffffff0;
227 }
228 
229 /*
230  * These two functions convert virtual addresses to PCI addresses and PCI
231  * addresses to virtual addresses.  Note that it is only legal to use these
232  * on memory obtained via get_zeroed_page or kmalloc.
233  */
234 unsigned long __virt_to_bus(unsigned long res)
235 {
236 	WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
237 
238 	return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
239 }
240 EXPORT_SYMBOL(__virt_to_bus);
241 
242 unsigned long __bus_to_virt(unsigned long res)
243 {
244 	res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
245 
246 	WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
247 
248 	return res;
249 }
250 EXPORT_SYMBOL(__bus_to_virt);
251 
252 unsigned long __pfn_to_bus(unsigned long pfn)
253 {
254 	return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
255 }
256 EXPORT_SYMBOL(__pfn_to_bus);
257 
258 unsigned long __bus_to_pfn(unsigned long bus)
259 {
260 	return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
261 }
262 EXPORT_SYMBOL(__bus_to_pfn);
263 
264 #endif
265