1 /*
2  *  linux/arch/arm/mach-footbridge/common.c
3  *
4  *  Copyright (C) 1998-2000 Russell King, Dave Gilbert.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/mm.h>
13 #include <linux/ioport.h>
14 #include <linux/list.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/spinlock.h>
18 #include <video/vga.h>
19 
20 #include <asm/pgtable.h>
21 #include <asm/page.h>
22 #include <asm/irq.h>
23 #include <asm/mach-types.h>
24 #include <asm/setup.h>
25 #include <asm/system_misc.h>
26 #include <asm/hardware/dec21285.h>
27 
28 #include <asm/mach/irq.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/pci.h>
31 
32 #include "common.h"
33 
34 unsigned int mem_fclk_21285 = 50000000;
35 
36 EXPORT_SYMBOL(mem_fclk_21285);
37 
38 static int __init early_fclk(char *arg)
39 {
40 	mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
41 	return 0;
42 }
43 
44 early_param("mem_fclk_21285", early_fclk);
45 
46 static int __init parse_tag_memclk(const struct tag *tag)
47 {
48 	mem_fclk_21285 = tag->u.memclk.fmemclk;
49 	return 0;
50 }
51 
52 __tagtable(ATAG_MEMCLK, parse_tag_memclk);
53 
54 /*
55  * Footbridge IRQ translation table
56  *  Converts from our IRQ numbers into FootBridge masks
57  */
58 static const int fb_irq_mask[] = {
59 	IRQ_MASK_UART_RX,	/*  0 */
60 	IRQ_MASK_UART_TX,	/*  1 */
61 	IRQ_MASK_TIMER1,	/*  2 */
62 	IRQ_MASK_TIMER2,	/*  3 */
63 	IRQ_MASK_TIMER3,	/*  4 */
64 	IRQ_MASK_IN0,		/*  5 */
65 	IRQ_MASK_IN1,		/*  6 */
66 	IRQ_MASK_IN2,		/*  7 */
67 	IRQ_MASK_IN3,		/*  8 */
68 	IRQ_MASK_DOORBELLHOST,	/*  9 */
69 	IRQ_MASK_DMA1,		/* 10 */
70 	IRQ_MASK_DMA2,		/* 11 */
71 	IRQ_MASK_PCI,		/* 12 */
72 	IRQ_MASK_SDRAMPARITY,	/* 13 */
73 	IRQ_MASK_I2OINPOST,	/* 14 */
74 	IRQ_MASK_PCI_ABORT,	/* 15 */
75 	IRQ_MASK_PCI_SERR,	/* 16 */
76 	IRQ_MASK_DISCARD_TIMER,	/* 17 */
77 	IRQ_MASK_PCI_DPERR,	/* 18 */
78 	IRQ_MASK_PCI_PERR,	/* 19 */
79 };
80 
81 static void fb_mask_irq(struct irq_data *d)
82 {
83 	*CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
84 }
85 
86 static void fb_unmask_irq(struct irq_data *d)
87 {
88 	*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
89 }
90 
91 static struct irq_chip fb_chip = {
92 	.irq_ack	= fb_mask_irq,
93 	.irq_mask	= fb_mask_irq,
94 	.irq_unmask	= fb_unmask_irq,
95 };
96 
97 static void __init __fb_init_irq(void)
98 {
99 	unsigned int irq;
100 
101 	/*
102 	 * setup DC21285 IRQs
103 	 */
104 	*CSR_IRQ_DISABLE = -1;
105 	*CSR_FIQ_DISABLE = -1;
106 
107 	for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
108 		irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
109 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 	}
111 }
112 
113 void __init footbridge_init_irq(void)
114 {
115 	__fb_init_irq();
116 
117 	if (!footbridge_cfn_mode())
118 		return;
119 
120 	if (machine_is_ebsa285())
121 		/* The following is dependent on which slot
122 		 * you plug the Southbridge card into.  We
123 		 * currently assume that you plug it into
124 		 * the right-hand most slot.
125 		 */
126 		isa_init_irq(IRQ_PCI);
127 
128 	if (machine_is_cats())
129 		isa_init_irq(IRQ_IN2);
130 
131 	if (machine_is_netwinder())
132 		isa_init_irq(IRQ_IN3);
133 }
134 
135 /*
136  * Common mapping for all systems.  Note that the outbound write flush is
137  * commented out since there is a "No Fix" problem with it.  Not mapping
138  * it means that we have extra bullet protection on our feet.
139  */
140 static struct map_desc fb_common_io_desc[] __initdata = {
141 	{
142 		.virtual	= ARMCSR_BASE,
143 		.pfn		= __phys_to_pfn(DC21285_ARMCSR_BASE),
144 		.length		= ARMCSR_SIZE,
145 		.type		= MT_DEVICE,
146 	}
147 };
148 
149 /*
150  * The mapping when the footbridge is in host mode.  We don't map any of
151  * this when we are in add-in mode.
152  */
153 static struct map_desc ebsa285_host_io_desc[] __initdata = {
154 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
155 	{
156 		.virtual	= PCIMEM_BASE,
157 		.pfn		= __phys_to_pfn(DC21285_PCI_MEM),
158 		.length		= PCIMEM_SIZE,
159 		.type		= MT_DEVICE,
160 	}, {
161 		.virtual	= PCICFG0_BASE,
162 		.pfn		= __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
163 		.length		= PCICFG0_SIZE,
164 		.type		= MT_DEVICE,
165 	}, {
166 		.virtual	= PCICFG1_BASE,
167 		.pfn		= __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
168 		.length		= PCICFG1_SIZE,
169 		.type		= MT_DEVICE,
170 	}, {
171 		.virtual	= PCIIACK_BASE,
172 		.pfn		= __phys_to_pfn(DC21285_PCI_IACK),
173 		.length		= PCIIACK_SIZE,
174 		.type		= MT_DEVICE,
175 	},
176 #endif
177 };
178 
179 void __init footbridge_map_io(void)
180 {
181 	/*
182 	 * Set up the common mapping first; we need this to
183 	 * determine whether we're in host mode or not.
184 	 */
185 	iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
186 
187 	/*
188 	 * Now, work out what we've got to map in addition on this
189 	 * platform.
190 	 */
191 	if (footbridge_cfn_mode()) {
192 		iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
193 		pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
194 	}
195 
196 	vga_base = PCIMEM_BASE;
197 }
198 
199 void footbridge_restart(enum reboot_mode mode, const char *cmd)
200 {
201 	if (mode == REBOOT_SOFT) {
202 		/* Jump into the ROM */
203 		soft_restart(0x41000000);
204 	} else {
205 		/*
206 		 * Force the watchdog to do a CPU reset.
207 		 *
208 		 * After making sure that the watchdog is disabled
209 		 * (so we can change the timer registers) we first
210 		 * enable the timer to autoreload itself.  Next, the
211 		 * timer interval is set really short and any
212 		 * current interrupt request is cleared (so we can
213 		 * see an edge transition).  Finally, TIMER4 is
214 		 * enabled as the watchdog.
215 		 */
216 		*CSR_SA110_CNTL &= ~(1 << 13);
217 		*CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
218 				   TIMER_CNTL_AUTORELOAD |
219 				   TIMER_CNTL_DIV16;
220 		*CSR_TIMER4_LOAD = 0x2;
221 		*CSR_TIMER4_CLR  = 0;
222 		*CSR_SA110_CNTL |= (1 << 13);
223 	}
224 }
225 
226 #ifdef CONFIG_FOOTBRIDGE_ADDIN
227 
228 static inline unsigned long fb_bus_sdram_offset(void)
229 {
230 	return *CSR_PCISDRAMBASE & 0xfffffff0;
231 }
232 
233 /*
234  * These two functions convert virtual addresses to PCI addresses and PCI
235  * addresses to virtual addresses.  Note that it is only legal to use these
236  * on memory obtained via get_zeroed_page or kmalloc.
237  */
238 unsigned long __virt_to_bus(unsigned long res)
239 {
240 	WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
241 
242 	return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
243 }
244 EXPORT_SYMBOL(__virt_to_bus);
245 
246 unsigned long __bus_to_virt(unsigned long res)
247 {
248 	res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
249 
250 	WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
251 
252 	return res;
253 }
254 EXPORT_SYMBOL(__bus_to_virt);
255 
256 unsigned long __pfn_to_bus(unsigned long pfn)
257 {
258 	return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
259 }
260 EXPORT_SYMBOL(__pfn_to_bus);
261 
262 unsigned long __bus_to_pfn(unsigned long bus)
263 {
264 	return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
265 }
266 EXPORT_SYMBOL(__bus_to_pfn);
267 
268 #endif
269