1 /* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Suspend support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqdomain.h> 24 #include <linux/of_address.h> 25 #include <linux/err.h> 26 #include <linux/regulator/machine.h> 27 #include <linux/soc/samsung/exynos-pmu.h> 28 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 30 #include <asm/cacheflush.h> 31 #include <asm/hardware/cache-l2x0.h> 32 #include <asm/firmware.h> 33 #include <asm/mcpm.h> 34 #include <asm/smp_scu.h> 35 #include <asm/suspend.h> 36 37 #include <mach/map.h> 38 39 #include <plat/pm-common.h> 40 41 #include "common.h" 42 43 #define REG_TABLE_END (-1U) 44 45 #define EXYNOS5420_CPU_STATE 0x28 46 47 /** 48 * struct exynos_wkup_irq - PMU IRQ to mask mapping 49 * @hwirq: Hardware IRQ signal of the PMU 50 * @mask: Mask in PMU wake-up mask register 51 */ 52 struct exynos_wkup_irq { 53 unsigned int hwirq; 54 u32 mask; 55 }; 56 57 struct exynos_pm_data { 58 const struct exynos_wkup_irq *wkup_irq; 59 unsigned int wake_disable_mask; 60 unsigned int *release_ret_regs; 61 62 void (*pm_prepare)(void); 63 void (*pm_resume_prepare)(void); 64 void (*pm_resume)(void); 65 int (*pm_suspend)(void); 66 int (*cpu_suspend)(unsigned long); 67 }; 68 69 static const struct exynos_pm_data *pm_data; 70 71 static int exynos5420_cpu_state; 72 static unsigned int exynos_pmu_spare3; 73 74 /* 75 * GIC wake-up support 76 */ 77 78 static u32 exynos_irqwake_intmask = 0xffffffff; 79 80 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 81 { 73, BIT(1) }, /* RTC alarm */ 82 { 74, BIT(2) }, /* RTC tick */ 83 { /* sentinel */ }, 84 }; 85 86 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 87 { 44, BIT(1) }, /* RTC alarm */ 88 { 45, BIT(2) }, /* RTC tick */ 89 { /* sentinel */ }, 90 }; 91 92 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 93 { 43, BIT(1) }, /* RTC alarm */ 94 { 44, BIT(2) }, /* RTC tick */ 95 { /* sentinel */ }, 96 }; 97 98 static unsigned int exynos_release_ret_regs[] = { 99 S5P_PAD_RET_MAUDIO_OPTION, 100 S5P_PAD_RET_GPIO_OPTION, 101 S5P_PAD_RET_UART_OPTION, 102 S5P_PAD_RET_MMCA_OPTION, 103 S5P_PAD_RET_MMCB_OPTION, 104 S5P_PAD_RET_EBIA_OPTION, 105 S5P_PAD_RET_EBIB_OPTION, 106 REG_TABLE_END, 107 }; 108 109 static unsigned int exynos3250_release_ret_regs[] = { 110 S5P_PAD_RET_MAUDIO_OPTION, 111 S5P_PAD_RET_GPIO_OPTION, 112 S5P_PAD_RET_UART_OPTION, 113 S5P_PAD_RET_MMCA_OPTION, 114 S5P_PAD_RET_MMCB_OPTION, 115 S5P_PAD_RET_EBIA_OPTION, 116 S5P_PAD_RET_EBIB_OPTION, 117 S5P_PAD_RET_MMC2_OPTION, 118 S5P_PAD_RET_SPI_OPTION, 119 REG_TABLE_END, 120 }; 121 122 static unsigned int exynos5420_release_ret_regs[] = { 123 EXYNOS_PAD_RET_DRAM_OPTION, 124 EXYNOS_PAD_RET_MAUDIO_OPTION, 125 EXYNOS_PAD_RET_JTAG_OPTION, 126 EXYNOS5420_PAD_RET_GPIO_OPTION, 127 EXYNOS5420_PAD_RET_UART_OPTION, 128 EXYNOS5420_PAD_RET_MMCA_OPTION, 129 EXYNOS5420_PAD_RET_MMCB_OPTION, 130 EXYNOS5420_PAD_RET_MMCC_OPTION, 131 EXYNOS5420_PAD_RET_HSI_OPTION, 132 EXYNOS_PAD_RET_EBIA_OPTION, 133 EXYNOS_PAD_RET_EBIB_OPTION, 134 EXYNOS5420_PAD_RET_SPI_OPTION, 135 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 136 REG_TABLE_END, 137 }; 138 139 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 140 { 141 const struct exynos_wkup_irq *wkup_irq; 142 143 if (!pm_data->wkup_irq) 144 return -ENOENT; 145 wkup_irq = pm_data->wkup_irq; 146 147 while (wkup_irq->mask) { 148 if (wkup_irq->hwirq == data->hwirq) { 149 if (!state) 150 exynos_irqwake_intmask |= wkup_irq->mask; 151 else 152 exynos_irqwake_intmask &= ~wkup_irq->mask; 153 return 0; 154 } 155 ++wkup_irq; 156 } 157 158 return -ENOENT; 159 } 160 161 static struct irq_chip exynos_pmu_chip = { 162 .name = "PMU", 163 .irq_eoi = irq_chip_eoi_parent, 164 .irq_mask = irq_chip_mask_parent, 165 .irq_unmask = irq_chip_unmask_parent, 166 .irq_retrigger = irq_chip_retrigger_hierarchy, 167 .irq_set_wake = exynos_irq_set_wake, 168 #ifdef CONFIG_SMP 169 .irq_set_affinity = irq_chip_set_affinity_parent, 170 #endif 171 }; 172 173 static int exynos_pmu_domain_translate(struct irq_domain *d, 174 struct irq_fwspec *fwspec, 175 unsigned long *hwirq, 176 unsigned int *type) 177 { 178 if (is_of_node(fwspec->fwnode)) { 179 if (fwspec->param_count != 3) 180 return -EINVAL; 181 182 /* No PPI should point to this domain */ 183 if (fwspec->param[0] != 0) 184 return -EINVAL; 185 186 *hwirq = fwspec->param[1]; 187 *type = fwspec->param[2]; 188 return 0; 189 } 190 191 return -EINVAL; 192 } 193 194 static int exynos_pmu_domain_alloc(struct irq_domain *domain, 195 unsigned int virq, 196 unsigned int nr_irqs, void *data) 197 { 198 struct irq_fwspec *fwspec = data; 199 struct irq_fwspec parent_fwspec; 200 irq_hw_number_t hwirq; 201 int i; 202 203 if (fwspec->param_count != 3) 204 return -EINVAL; /* Not GIC compliant */ 205 if (fwspec->param[0] != 0) 206 return -EINVAL; /* No PPI should point to this domain */ 207 208 hwirq = fwspec->param[1]; 209 210 for (i = 0; i < nr_irqs; i++) 211 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 212 &exynos_pmu_chip, NULL); 213 214 parent_fwspec = *fwspec; 215 parent_fwspec.fwnode = domain->parent->fwnode; 216 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 217 &parent_fwspec); 218 } 219 220 static const struct irq_domain_ops exynos_pmu_domain_ops = { 221 .translate = exynos_pmu_domain_translate, 222 .alloc = exynos_pmu_domain_alloc, 223 .free = irq_domain_free_irqs_common, 224 }; 225 226 static int __init exynos_pmu_irq_init(struct device_node *node, 227 struct device_node *parent) 228 { 229 struct irq_domain *parent_domain, *domain; 230 231 if (!parent) { 232 pr_err("%s: no parent, giving up\n", node->full_name); 233 return -ENODEV; 234 } 235 236 parent_domain = irq_find_host(parent); 237 if (!parent_domain) { 238 pr_err("%s: unable to obtain parent domain\n", node->full_name); 239 return -ENXIO; 240 } 241 242 pmu_base_addr = of_iomap(node, 0); 243 244 if (!pmu_base_addr) { 245 pr_err("%s: failed to find exynos pmu register\n", 246 node->full_name); 247 return -ENOMEM; 248 } 249 250 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, 251 node, &exynos_pmu_domain_ops, 252 NULL); 253 if (!domain) { 254 iounmap(pmu_base_addr); 255 return -ENOMEM; 256 } 257 258 /* 259 * Clear the OF_POPULATED flag set in of_irq_init so that 260 * later the Exynos PMU platform device won't be skipped. 261 */ 262 of_node_clear_flag(node, OF_POPULATED); 263 264 return 0; 265 } 266 267 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init) 268 269 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); 270 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); 271 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); 272 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); 273 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); 274 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); 275 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); 276 277 static int exynos_cpu_do_idle(void) 278 { 279 /* issue the standby signal into the pm unit. */ 280 cpu_do_idle(); 281 282 pr_info("Failed to suspend the system\n"); 283 return 1; /* Aborting suspend */ 284 } 285 static void exynos_flush_cache_all(void) 286 { 287 flush_cache_all(); 288 outer_flush_all(); 289 } 290 291 static int exynos_cpu_suspend(unsigned long arg) 292 { 293 exynos_flush_cache_all(); 294 return exynos_cpu_do_idle(); 295 } 296 297 static int exynos3250_cpu_suspend(unsigned long arg) 298 { 299 flush_cache_all(); 300 return exynos_cpu_do_idle(); 301 } 302 303 static int exynos5420_cpu_suspend(unsigned long arg) 304 { 305 /* MCPM works with HW CPU identifiers */ 306 unsigned int mpidr = read_cpuid_mpidr(); 307 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 308 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 309 310 writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); 311 312 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { 313 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); 314 mcpm_cpu_suspend(); 315 } 316 317 pr_info("Failed to suspend the system\n"); 318 319 /* return value != 0 means failure */ 320 return 1; 321 } 322 323 static void exynos_pm_set_wakeup_mask(void) 324 { 325 /* Set wake-up mask registers */ 326 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 327 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 328 } 329 330 static void exynos_pm_enter_sleep_mode(void) 331 { 332 /* Set value of power down register for sleep mode */ 333 exynos_sys_powerdown_conf(SYS_SLEEP); 334 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1); 335 } 336 337 static void exynos_pm_prepare(void) 338 { 339 exynos_set_delayed_reset_assertion(false); 340 341 /* Set wake-up mask registers */ 342 exynos_pm_set_wakeup_mask(); 343 344 exynos_pm_enter_sleep_mode(); 345 346 /* ensure at least INFORM0 has the resume address */ 347 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 348 } 349 350 static void exynos3250_pm_prepare(void) 351 { 352 unsigned int tmp; 353 354 /* Set wake-up mask registers */ 355 exynos_pm_set_wakeup_mask(); 356 357 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); 358 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 359 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); 360 361 exynos_pm_enter_sleep_mode(); 362 363 /* ensure at least INFORM0 has the resume address */ 364 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 365 } 366 367 static void exynos5420_pm_prepare(void) 368 { 369 unsigned int tmp; 370 371 /* Set wake-up mask registers */ 372 exynos_pm_set_wakeup_mask(); 373 374 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); 375 /* 376 * The cpu state needs to be saved and restored so that the 377 * secondary CPUs will enter low power start. Though the U-Boot 378 * is setting the cpu state with low power flag, the kernel 379 * needs to restore it back in case, the primary cpu fails to 380 * suspend for any reason. 381 */ 382 exynos5420_cpu_state = readl_relaxed(sysram_base_addr + 383 EXYNOS5420_CPU_STATE); 384 385 exynos_pm_enter_sleep_mode(); 386 387 /* ensure at least INFORM0 has the resume address */ 388 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 389 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); 390 391 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); 392 tmp &= ~EXYNOS5_USE_RETENTION; 393 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); 394 395 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 396 tmp |= EXYNOS5420_UFS; 397 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 398 399 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); 400 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; 401 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); 402 403 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 404 tmp |= EXYNOS5420_EMULATION; 405 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 406 407 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 408 tmp |= EXYNOS5420_EMULATION; 409 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 410 } 411 412 413 static int exynos_pm_suspend(void) 414 { 415 exynos_pm_central_suspend(); 416 417 /* Setting SEQ_OPTION register */ 418 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 419 S5P_CENTRAL_SEQ_OPTION); 420 421 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 422 exynos_cpu_save_register(); 423 424 return 0; 425 } 426 427 static int exynos5420_pm_suspend(void) 428 { 429 u32 this_cluster; 430 431 exynos_pm_central_suspend(); 432 433 /* Setting SEQ_OPTION register */ 434 435 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 436 if (!this_cluster) 437 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, 438 S5P_CENTRAL_SEQ_OPTION); 439 else 440 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, 441 S5P_CENTRAL_SEQ_OPTION); 442 return 0; 443 } 444 445 static void exynos_pm_release_retention(void) 446 { 447 unsigned int i; 448 449 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) 450 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, 451 pm_data->release_ret_regs[i]); 452 } 453 454 static void exynos_pm_resume(void) 455 { 456 u32 cpuid = read_cpuid_part(); 457 458 if (exynos_pm_central_resume()) 459 goto early_wakeup; 460 461 /* For release retention */ 462 exynos_pm_release_retention(); 463 464 if (cpuid == ARM_CPU_PART_CORTEX_A9) 465 scu_enable(S5P_VA_SCU); 466 467 if (call_firmware_op(resume) == -ENOSYS 468 && cpuid == ARM_CPU_PART_CORTEX_A9) 469 exynos_cpu_restore_register(); 470 471 early_wakeup: 472 473 /* Clear SLEEP mode set in INFORM1 */ 474 pmu_raw_writel(0x0, S5P_INFORM1); 475 exynos_set_delayed_reset_assertion(true); 476 } 477 478 static void exynos3250_pm_resume(void) 479 { 480 u32 cpuid = read_cpuid_part(); 481 482 if (exynos_pm_central_resume()) 483 goto early_wakeup; 484 485 /* For release retention */ 486 exynos_pm_release_retention(); 487 488 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); 489 490 if (call_firmware_op(resume) == -ENOSYS 491 && cpuid == ARM_CPU_PART_CORTEX_A9) 492 exynos_cpu_restore_register(); 493 494 early_wakeup: 495 496 /* Clear SLEEP mode set in INFORM1 */ 497 pmu_raw_writel(0x0, S5P_INFORM1); 498 } 499 500 static void exynos5420_prepare_pm_resume(void) 501 { 502 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 503 WARN_ON(mcpm_cpu_powered_up()); 504 } 505 506 static void exynos5420_pm_resume(void) 507 { 508 unsigned long tmp; 509 510 /* Restore the CPU0 low power state register */ 511 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); 512 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, 513 EXYNOS5_ARM_CORE0_SYS_PWR_REG); 514 515 /* Restore the sysram cpu state register */ 516 writel_relaxed(exynos5420_cpu_state, 517 sysram_base_addr + EXYNOS5420_CPU_STATE); 518 519 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, 520 S5P_CENTRAL_SEQ_OPTION); 521 522 if (exynos_pm_central_resume()) 523 goto early_wakeup; 524 525 /* For release retention */ 526 exynos_pm_release_retention(); 527 528 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); 529 530 early_wakeup: 531 532 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 533 tmp &= ~EXYNOS5420_UFS; 534 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 535 536 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 537 tmp &= ~EXYNOS5420_EMULATION; 538 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 539 540 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 541 tmp &= ~EXYNOS5420_EMULATION; 542 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 543 544 /* Clear SLEEP mode set in INFORM1 */ 545 pmu_raw_writel(0x0, S5P_INFORM1); 546 } 547 548 /* 549 * Suspend Ops 550 */ 551 552 static int exynos_suspend_enter(suspend_state_t state) 553 { 554 int ret; 555 556 s3c_pm_debug_init(); 557 558 S3C_PMDBG("%s: suspending the system...\n", __func__); 559 560 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 561 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 562 563 if (exynos_irqwake_intmask == -1U 564 && exynos_get_eint_wake_mask() == -1U) { 565 pr_err("%s: No wake-up sources!\n", __func__); 566 pr_err("%s: Aborting sleep\n", __func__); 567 return -EINVAL; 568 } 569 570 s3c_pm_save_uarts(); 571 if (pm_data->pm_prepare) 572 pm_data->pm_prepare(); 573 flush_cache_all(); 574 s3c_pm_check_store(); 575 576 ret = call_firmware_op(suspend); 577 if (ret == -ENOSYS) 578 ret = cpu_suspend(0, pm_data->cpu_suspend); 579 if (ret) 580 return ret; 581 582 if (pm_data->pm_resume_prepare) 583 pm_data->pm_resume_prepare(); 584 s3c_pm_restore_uarts(); 585 586 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 587 pmu_raw_readl(S5P_WAKEUP_STAT)); 588 589 s3c_pm_check_restore(); 590 591 S3C_PMDBG("%s: resuming the system...\n", __func__); 592 593 return 0; 594 } 595 596 static int exynos_suspend_prepare(void) 597 { 598 int ret; 599 600 /* 601 * REVISIT: It would be better if struct platform_suspend_ops 602 * .prepare handler get the suspend_state_t as a parameter to 603 * avoid hard-coding the suspend to mem state. It's safe to do 604 * it now only because the suspend_valid_only_mem function is 605 * used as the .valid callback used to check if a given state 606 * is supported by the platform anyways. 607 */ 608 ret = regulator_suspend_prepare(PM_SUSPEND_MEM); 609 if (ret) { 610 pr_err("Failed to prepare regulators for suspend (%d)\n", ret); 611 return ret; 612 } 613 614 s3c_pm_check_prepare(); 615 616 return 0; 617 } 618 619 static void exynos_suspend_finish(void) 620 { 621 int ret; 622 623 s3c_pm_check_cleanup(); 624 625 ret = regulator_suspend_finish(); 626 if (ret) 627 pr_warn("Failed to resume regulators from suspend (%d)\n", ret); 628 } 629 630 static const struct platform_suspend_ops exynos_suspend_ops = { 631 .enter = exynos_suspend_enter, 632 .prepare = exynos_suspend_prepare, 633 .finish = exynos_suspend_finish, 634 .valid = suspend_valid_only_mem, 635 }; 636 637 static const struct exynos_pm_data exynos3250_pm_data = { 638 .wkup_irq = exynos3250_wkup_irq, 639 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 640 .release_ret_regs = exynos3250_release_ret_regs, 641 .pm_suspend = exynos_pm_suspend, 642 .pm_resume = exynos3250_pm_resume, 643 .pm_prepare = exynos3250_pm_prepare, 644 .cpu_suspend = exynos3250_cpu_suspend, 645 }; 646 647 static const struct exynos_pm_data exynos4_pm_data = { 648 .wkup_irq = exynos4_wkup_irq, 649 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 650 .release_ret_regs = exynos_release_ret_regs, 651 .pm_suspend = exynos_pm_suspend, 652 .pm_resume = exynos_pm_resume, 653 .pm_prepare = exynos_pm_prepare, 654 .cpu_suspend = exynos_cpu_suspend, 655 }; 656 657 static const struct exynos_pm_data exynos5250_pm_data = { 658 .wkup_irq = exynos5250_wkup_irq, 659 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 660 .release_ret_regs = exynos_release_ret_regs, 661 .pm_suspend = exynos_pm_suspend, 662 .pm_resume = exynos_pm_resume, 663 .pm_prepare = exynos_pm_prepare, 664 .cpu_suspend = exynos_cpu_suspend, 665 }; 666 667 static const struct exynos_pm_data exynos5420_pm_data = { 668 .wkup_irq = exynos5250_wkup_irq, 669 .wake_disable_mask = (0x7F << 7) | (0x1F << 1), 670 .release_ret_regs = exynos5420_release_ret_regs, 671 .pm_resume_prepare = exynos5420_prepare_pm_resume, 672 .pm_resume = exynos5420_pm_resume, 673 .pm_suspend = exynos5420_pm_suspend, 674 .pm_prepare = exynos5420_pm_prepare, 675 .cpu_suspend = exynos5420_cpu_suspend, 676 }; 677 678 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { 679 { 680 .compatible = "samsung,exynos3250-pmu", 681 .data = &exynos3250_pm_data, 682 }, { 683 .compatible = "samsung,exynos4210-pmu", 684 .data = &exynos4_pm_data, 685 }, { 686 .compatible = "samsung,exynos4212-pmu", 687 .data = &exynos4_pm_data, 688 }, { 689 .compatible = "samsung,exynos4412-pmu", 690 .data = &exynos4_pm_data, 691 }, { 692 .compatible = "samsung,exynos5250-pmu", 693 .data = &exynos5250_pm_data, 694 }, { 695 .compatible = "samsung,exynos5420-pmu", 696 .data = &exynos5420_pm_data, 697 }, 698 { /*sentinel*/ }, 699 }; 700 701 static struct syscore_ops exynos_pm_syscore_ops; 702 703 void __init exynos_pm_init(void) 704 { 705 const struct of_device_id *match; 706 struct device_node *np; 707 u32 tmp; 708 709 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); 710 if (!np) { 711 pr_err("Failed to find PMU node\n"); 712 return; 713 } 714 715 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 716 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 717 return; 718 } 719 720 pm_data = (const struct exynos_pm_data *) match->data; 721 722 /* All wakeup disable */ 723 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 724 tmp |= pm_data->wake_disable_mask; 725 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 726 727 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; 728 exynos_pm_syscore_ops.resume = pm_data->pm_resume; 729 730 register_syscore_ops(&exynos_pm_syscore_ops); 731 suspend_set_ops(&exynos_suspend_ops); 732 } 733