1 /* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Suspend support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/of_address.h> 24 #include <linux/err.h> 25 #include <linux/regulator/machine.h> 26 27 #include <asm/cacheflush.h> 28 #include <asm/hardware/cache-l2x0.h> 29 #include <asm/firmware.h> 30 #include <asm/mcpm.h> 31 #include <asm/smp_scu.h> 32 #include <asm/suspend.h> 33 34 #include <plat/pm-common.h> 35 36 #include "common.h" 37 #include "exynos-pmu.h" 38 #include "regs-pmu.h" 39 #include "regs-srom.h" 40 41 #define REG_TABLE_END (-1U) 42 43 #define EXYNOS5420_CPU_STATE 0x28 44 45 /** 46 * struct exynos_wkup_irq - PMU IRQ to mask mapping 47 * @hwirq: Hardware IRQ signal of the PMU 48 * @mask: Mask in PMU wake-up mask register 49 */ 50 struct exynos_wkup_irq { 51 unsigned int hwirq; 52 u32 mask; 53 }; 54 55 static struct sleep_save exynos_core_save[] = { 56 /* SROM side */ 57 SAVE_ITEM(S5P_SROM_BW), 58 SAVE_ITEM(S5P_SROM_BC0), 59 SAVE_ITEM(S5P_SROM_BC1), 60 SAVE_ITEM(S5P_SROM_BC2), 61 SAVE_ITEM(S5P_SROM_BC3), 62 }; 63 64 struct exynos_pm_data { 65 const struct exynos_wkup_irq *wkup_irq; 66 unsigned int wake_disable_mask; 67 unsigned int *release_ret_regs; 68 69 void (*pm_prepare)(void); 70 void (*pm_resume_prepare)(void); 71 void (*pm_resume)(void); 72 int (*pm_suspend)(void); 73 int (*cpu_suspend)(unsigned long); 74 }; 75 76 static const struct exynos_pm_data *pm_data; 77 78 static int exynos5420_cpu_state; 79 static unsigned int exynos_pmu_spare3; 80 81 /* 82 * GIC wake-up support 83 */ 84 85 static u32 exynos_irqwake_intmask = 0xffffffff; 86 87 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 88 { 73, BIT(1) }, /* RTC alarm */ 89 { 74, BIT(2) }, /* RTC tick */ 90 { /* sentinel */ }, 91 }; 92 93 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 94 { 44, BIT(1) }, /* RTC alarm */ 95 { 45, BIT(2) }, /* RTC tick */ 96 { /* sentinel */ }, 97 }; 98 99 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 100 { 43, BIT(1) }, /* RTC alarm */ 101 { 44, BIT(2) }, /* RTC tick */ 102 { /* sentinel */ }, 103 }; 104 105 static unsigned int exynos_release_ret_regs[] = { 106 S5P_PAD_RET_MAUDIO_OPTION, 107 S5P_PAD_RET_GPIO_OPTION, 108 S5P_PAD_RET_UART_OPTION, 109 S5P_PAD_RET_MMCA_OPTION, 110 S5P_PAD_RET_MMCB_OPTION, 111 S5P_PAD_RET_EBIA_OPTION, 112 S5P_PAD_RET_EBIB_OPTION, 113 REG_TABLE_END, 114 }; 115 116 static unsigned int exynos3250_release_ret_regs[] = { 117 S5P_PAD_RET_MAUDIO_OPTION, 118 S5P_PAD_RET_GPIO_OPTION, 119 S5P_PAD_RET_UART_OPTION, 120 S5P_PAD_RET_MMCA_OPTION, 121 S5P_PAD_RET_MMCB_OPTION, 122 S5P_PAD_RET_EBIA_OPTION, 123 S5P_PAD_RET_EBIB_OPTION, 124 S5P_PAD_RET_MMC2_OPTION, 125 S5P_PAD_RET_SPI_OPTION, 126 REG_TABLE_END, 127 }; 128 129 static unsigned int exynos5420_release_ret_regs[] = { 130 EXYNOS_PAD_RET_DRAM_OPTION, 131 EXYNOS_PAD_RET_MAUDIO_OPTION, 132 EXYNOS_PAD_RET_JTAG_OPTION, 133 EXYNOS5420_PAD_RET_GPIO_OPTION, 134 EXYNOS5420_PAD_RET_UART_OPTION, 135 EXYNOS5420_PAD_RET_MMCA_OPTION, 136 EXYNOS5420_PAD_RET_MMCB_OPTION, 137 EXYNOS5420_PAD_RET_MMCC_OPTION, 138 EXYNOS5420_PAD_RET_HSI_OPTION, 139 EXYNOS_PAD_RET_EBIA_OPTION, 140 EXYNOS_PAD_RET_EBIB_OPTION, 141 EXYNOS5420_PAD_RET_SPI_OPTION, 142 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 143 REG_TABLE_END, 144 }; 145 146 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 147 { 148 const struct exynos_wkup_irq *wkup_irq; 149 150 if (!pm_data->wkup_irq) 151 return -ENOENT; 152 wkup_irq = pm_data->wkup_irq; 153 154 while (wkup_irq->mask) { 155 if (wkup_irq->hwirq == data->hwirq) { 156 if (!state) 157 exynos_irqwake_intmask |= wkup_irq->mask; 158 else 159 exynos_irqwake_intmask &= ~wkup_irq->mask; 160 return 0; 161 } 162 ++wkup_irq; 163 } 164 165 return -ENOENT; 166 } 167 168 static struct irq_chip exynos_pmu_chip = { 169 .name = "PMU", 170 .irq_eoi = irq_chip_eoi_parent, 171 .irq_mask = irq_chip_mask_parent, 172 .irq_unmask = irq_chip_unmask_parent, 173 .irq_retrigger = irq_chip_retrigger_hierarchy, 174 .irq_set_wake = exynos_irq_set_wake, 175 #ifdef CONFIG_SMP 176 .irq_set_affinity = irq_chip_set_affinity_parent, 177 #endif 178 }; 179 180 static int exynos_pmu_domain_xlate(struct irq_domain *domain, 181 struct device_node *controller, 182 const u32 *intspec, 183 unsigned int intsize, 184 unsigned long *out_hwirq, 185 unsigned int *out_type) 186 { 187 if (domain->of_node != controller) 188 return -EINVAL; /* Shouldn't happen, really... */ 189 if (intsize != 3) 190 return -EINVAL; /* Not GIC compliant */ 191 if (intspec[0] != 0) 192 return -EINVAL; /* No PPI should point to this domain */ 193 194 *out_hwirq = intspec[1]; 195 *out_type = intspec[2]; 196 return 0; 197 } 198 199 static int exynos_pmu_domain_alloc(struct irq_domain *domain, 200 unsigned int virq, 201 unsigned int nr_irqs, void *data) 202 { 203 struct of_phandle_args *args = data; 204 struct of_phandle_args parent_args; 205 irq_hw_number_t hwirq; 206 int i; 207 208 if (args->args_count != 3) 209 return -EINVAL; /* Not GIC compliant */ 210 if (args->args[0] != 0) 211 return -EINVAL; /* No PPI should point to this domain */ 212 213 hwirq = args->args[1]; 214 215 for (i = 0; i < nr_irqs; i++) 216 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 217 &exynos_pmu_chip, NULL); 218 219 parent_args = *args; 220 parent_args.np = domain->parent->of_node; 221 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); 222 } 223 224 static const struct irq_domain_ops exynos_pmu_domain_ops = { 225 .xlate = exynos_pmu_domain_xlate, 226 .alloc = exynos_pmu_domain_alloc, 227 .free = irq_domain_free_irqs_common, 228 }; 229 230 static int __init exynos_pmu_irq_init(struct device_node *node, 231 struct device_node *parent) 232 { 233 struct irq_domain *parent_domain, *domain; 234 235 if (!parent) { 236 pr_err("%s: no parent, giving up\n", node->full_name); 237 return -ENODEV; 238 } 239 240 parent_domain = irq_find_host(parent); 241 if (!parent_domain) { 242 pr_err("%s: unable to obtain parent domain\n", node->full_name); 243 return -ENXIO; 244 } 245 246 pmu_base_addr = of_iomap(node, 0); 247 248 if (!pmu_base_addr) { 249 pr_err("%s: failed to find exynos pmu register\n", 250 node->full_name); 251 return -ENOMEM; 252 } 253 254 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, 255 node, &exynos_pmu_domain_ops, 256 NULL); 257 if (!domain) { 258 iounmap(pmu_base_addr); 259 return -ENOMEM; 260 } 261 262 return 0; 263 } 264 265 #define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init) 266 267 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); 268 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); 269 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); 270 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); 271 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); 272 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); 273 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); 274 275 static int exynos_cpu_do_idle(void) 276 { 277 /* issue the standby signal into the pm unit. */ 278 cpu_do_idle(); 279 280 pr_info("Failed to suspend the system\n"); 281 return 1; /* Aborting suspend */ 282 } 283 static void exynos_flush_cache_all(void) 284 { 285 flush_cache_all(); 286 outer_flush_all(); 287 } 288 289 static int exynos_cpu_suspend(unsigned long arg) 290 { 291 exynos_flush_cache_all(); 292 return exynos_cpu_do_idle(); 293 } 294 295 static int exynos3250_cpu_suspend(unsigned long arg) 296 { 297 flush_cache_all(); 298 return exynos_cpu_do_idle(); 299 } 300 301 static int exynos5420_cpu_suspend(unsigned long arg) 302 { 303 /* MCPM works with HW CPU identifiers */ 304 unsigned int mpidr = read_cpuid_mpidr(); 305 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 306 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 307 308 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); 309 310 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { 311 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); 312 mcpm_cpu_suspend(); 313 } 314 315 pr_info("Failed to suspend the system\n"); 316 317 /* return value != 0 means failure */ 318 return 1; 319 } 320 321 static void exynos_pm_set_wakeup_mask(void) 322 { 323 /* Set wake-up mask registers */ 324 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 325 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 326 } 327 328 static void exynos_pm_enter_sleep_mode(void) 329 { 330 /* Set value of power down register for sleep mode */ 331 exynos_sys_powerdown_conf(SYS_SLEEP); 332 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1); 333 } 334 335 static void exynos_pm_prepare(void) 336 { 337 exynos_set_delayed_reset_assertion(false); 338 339 /* Set wake-up mask registers */ 340 exynos_pm_set_wakeup_mask(); 341 342 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 343 344 exynos_pm_enter_sleep_mode(); 345 346 /* ensure at least INFORM0 has the resume address */ 347 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 348 } 349 350 static void exynos3250_pm_prepare(void) 351 { 352 unsigned int tmp; 353 354 /* Set wake-up mask registers */ 355 exynos_pm_set_wakeup_mask(); 356 357 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); 358 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 359 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); 360 361 exynos_pm_enter_sleep_mode(); 362 363 /* ensure at least INFORM0 has the resume address */ 364 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 365 } 366 367 static void exynos5420_pm_prepare(void) 368 { 369 unsigned int tmp; 370 371 /* Set wake-up mask registers */ 372 exynos_pm_set_wakeup_mask(); 373 374 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 375 376 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); 377 /* 378 * The cpu state needs to be saved and restored so that the 379 * secondary CPUs will enter low power start. Though the U-Boot 380 * is setting the cpu state with low power flag, the kernel 381 * needs to restore it back in case, the primary cpu fails to 382 * suspend for any reason. 383 */ 384 exynos5420_cpu_state = __raw_readl(sysram_base_addr + 385 EXYNOS5420_CPU_STATE); 386 387 exynos_pm_enter_sleep_mode(); 388 389 /* ensure at least INFORM0 has the resume address */ 390 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 391 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); 392 393 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); 394 tmp &= ~EXYNOS5_USE_RETENTION; 395 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); 396 397 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 398 tmp |= EXYNOS5420_UFS; 399 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 400 401 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); 402 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; 403 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); 404 405 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 406 tmp |= EXYNOS5420_EMULATION; 407 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 408 409 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 410 tmp |= EXYNOS5420_EMULATION; 411 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 412 } 413 414 415 static int exynos_pm_suspend(void) 416 { 417 exynos_pm_central_suspend(); 418 419 /* Setting SEQ_OPTION register */ 420 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 421 S5P_CENTRAL_SEQ_OPTION); 422 423 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 424 exynos_cpu_save_register(); 425 426 return 0; 427 } 428 429 static int exynos5420_pm_suspend(void) 430 { 431 u32 this_cluster; 432 433 exynos_pm_central_suspend(); 434 435 /* Setting SEQ_OPTION register */ 436 437 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 438 if (!this_cluster) 439 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, 440 S5P_CENTRAL_SEQ_OPTION); 441 else 442 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, 443 S5P_CENTRAL_SEQ_OPTION); 444 return 0; 445 } 446 447 static void exynos_pm_release_retention(void) 448 { 449 unsigned int i; 450 451 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) 452 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, 453 pm_data->release_ret_regs[i]); 454 } 455 456 static void exynos_pm_resume(void) 457 { 458 u32 cpuid = read_cpuid_part(); 459 460 if (exynos_pm_central_resume()) 461 goto early_wakeup; 462 463 /* For release retention */ 464 exynos_pm_release_retention(); 465 466 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 467 468 if (cpuid == ARM_CPU_PART_CORTEX_A9) 469 scu_enable(S5P_VA_SCU); 470 471 if (call_firmware_op(resume) == -ENOSYS 472 && cpuid == ARM_CPU_PART_CORTEX_A9) 473 exynos_cpu_restore_register(); 474 475 early_wakeup: 476 477 /* Clear SLEEP mode set in INFORM1 */ 478 pmu_raw_writel(0x0, S5P_INFORM1); 479 exynos_set_delayed_reset_assertion(true); 480 } 481 482 static void exynos3250_pm_resume(void) 483 { 484 u32 cpuid = read_cpuid_part(); 485 486 if (exynos_pm_central_resume()) 487 goto early_wakeup; 488 489 /* For release retention */ 490 exynos_pm_release_retention(); 491 492 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); 493 494 if (call_firmware_op(resume) == -ENOSYS 495 && cpuid == ARM_CPU_PART_CORTEX_A9) 496 exynos_cpu_restore_register(); 497 498 early_wakeup: 499 500 /* Clear SLEEP mode set in INFORM1 */ 501 pmu_raw_writel(0x0, S5P_INFORM1); 502 } 503 504 static void exynos5420_prepare_pm_resume(void) 505 { 506 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 507 WARN_ON(mcpm_cpu_powered_up()); 508 } 509 510 static void exynos5420_pm_resume(void) 511 { 512 unsigned long tmp; 513 514 /* Restore the CPU0 low power state register */ 515 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); 516 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, 517 EXYNOS5_ARM_CORE0_SYS_PWR_REG); 518 519 /* Restore the sysram cpu state register */ 520 __raw_writel(exynos5420_cpu_state, 521 sysram_base_addr + EXYNOS5420_CPU_STATE); 522 523 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, 524 S5P_CENTRAL_SEQ_OPTION); 525 526 if (exynos_pm_central_resume()) 527 goto early_wakeup; 528 529 /* For release retention */ 530 exynos_pm_release_retention(); 531 532 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); 533 534 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 535 536 early_wakeup: 537 538 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 539 tmp &= ~EXYNOS5420_UFS; 540 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 541 542 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 543 tmp &= ~EXYNOS5420_EMULATION; 544 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 545 546 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 547 tmp &= ~EXYNOS5420_EMULATION; 548 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 549 550 /* Clear SLEEP mode set in INFORM1 */ 551 pmu_raw_writel(0x0, S5P_INFORM1); 552 } 553 554 /* 555 * Suspend Ops 556 */ 557 558 static int exynos_suspend_enter(suspend_state_t state) 559 { 560 int ret; 561 562 s3c_pm_debug_init(); 563 564 S3C_PMDBG("%s: suspending the system...\n", __func__); 565 566 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 567 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 568 569 if (exynos_irqwake_intmask == -1U 570 && exynos_get_eint_wake_mask() == -1U) { 571 pr_err("%s: No wake-up sources!\n", __func__); 572 pr_err("%s: Aborting sleep\n", __func__); 573 return -EINVAL; 574 } 575 576 s3c_pm_save_uarts(); 577 if (pm_data->pm_prepare) 578 pm_data->pm_prepare(); 579 flush_cache_all(); 580 s3c_pm_check_store(); 581 582 ret = call_firmware_op(suspend); 583 if (ret == -ENOSYS) 584 ret = cpu_suspend(0, pm_data->cpu_suspend); 585 if (ret) 586 return ret; 587 588 if (pm_data->pm_resume_prepare) 589 pm_data->pm_resume_prepare(); 590 s3c_pm_restore_uarts(); 591 592 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 593 pmu_raw_readl(S5P_WAKEUP_STAT)); 594 595 s3c_pm_check_restore(); 596 597 S3C_PMDBG("%s: resuming the system...\n", __func__); 598 599 return 0; 600 } 601 602 static int exynos_suspend_prepare(void) 603 { 604 int ret; 605 606 /* 607 * REVISIT: It would be better if struct platform_suspend_ops 608 * .prepare handler get the suspend_state_t as a parameter to 609 * avoid hard-coding the suspend to mem state. It's safe to do 610 * it now only because the suspend_valid_only_mem function is 611 * used as the .valid callback used to check if a given state 612 * is supported by the platform anyways. 613 */ 614 ret = regulator_suspend_prepare(PM_SUSPEND_MEM); 615 if (ret) { 616 pr_err("Failed to prepare regulators for suspend (%d)\n", ret); 617 return ret; 618 } 619 620 s3c_pm_check_prepare(); 621 622 return 0; 623 } 624 625 static void exynos_suspend_finish(void) 626 { 627 int ret; 628 629 s3c_pm_check_cleanup(); 630 631 ret = regulator_suspend_finish(); 632 if (ret) 633 pr_warn("Failed to resume regulators from suspend (%d)\n", ret); 634 } 635 636 static const struct platform_suspend_ops exynos_suspend_ops = { 637 .enter = exynos_suspend_enter, 638 .prepare = exynos_suspend_prepare, 639 .finish = exynos_suspend_finish, 640 .valid = suspend_valid_only_mem, 641 }; 642 643 static const struct exynos_pm_data exynos3250_pm_data = { 644 .wkup_irq = exynos3250_wkup_irq, 645 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 646 .release_ret_regs = exynos3250_release_ret_regs, 647 .pm_suspend = exynos_pm_suspend, 648 .pm_resume = exynos3250_pm_resume, 649 .pm_prepare = exynos3250_pm_prepare, 650 .cpu_suspend = exynos3250_cpu_suspend, 651 }; 652 653 static const struct exynos_pm_data exynos4_pm_data = { 654 .wkup_irq = exynos4_wkup_irq, 655 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 656 .release_ret_regs = exynos_release_ret_regs, 657 .pm_suspend = exynos_pm_suspend, 658 .pm_resume = exynos_pm_resume, 659 .pm_prepare = exynos_pm_prepare, 660 .cpu_suspend = exynos_cpu_suspend, 661 }; 662 663 static const struct exynos_pm_data exynos5250_pm_data = { 664 .wkup_irq = exynos5250_wkup_irq, 665 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 666 .release_ret_regs = exynos_release_ret_regs, 667 .pm_suspend = exynos_pm_suspend, 668 .pm_resume = exynos_pm_resume, 669 .pm_prepare = exynos_pm_prepare, 670 .cpu_suspend = exynos_cpu_suspend, 671 }; 672 673 static const struct exynos_pm_data exynos5420_pm_data = { 674 .wkup_irq = exynos5250_wkup_irq, 675 .wake_disable_mask = (0x7F << 7) | (0x1F << 1), 676 .release_ret_regs = exynos5420_release_ret_regs, 677 .pm_resume_prepare = exynos5420_prepare_pm_resume, 678 .pm_resume = exynos5420_pm_resume, 679 .pm_suspend = exynos5420_pm_suspend, 680 .pm_prepare = exynos5420_pm_prepare, 681 .cpu_suspend = exynos5420_cpu_suspend, 682 }; 683 684 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { 685 { 686 .compatible = "samsung,exynos3250-pmu", 687 .data = &exynos3250_pm_data, 688 }, { 689 .compatible = "samsung,exynos4210-pmu", 690 .data = &exynos4_pm_data, 691 }, { 692 .compatible = "samsung,exynos4212-pmu", 693 .data = &exynos4_pm_data, 694 }, { 695 .compatible = "samsung,exynos4412-pmu", 696 .data = &exynos4_pm_data, 697 }, { 698 .compatible = "samsung,exynos5250-pmu", 699 .data = &exynos5250_pm_data, 700 }, { 701 .compatible = "samsung,exynos5420-pmu", 702 .data = &exynos5420_pm_data, 703 }, 704 { /*sentinel*/ }, 705 }; 706 707 static struct syscore_ops exynos_pm_syscore_ops; 708 709 void __init exynos_pm_init(void) 710 { 711 const struct of_device_id *match; 712 struct device_node *np; 713 u32 tmp; 714 715 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); 716 if (!np) { 717 pr_err("Failed to find PMU node\n"); 718 return; 719 } 720 721 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 722 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 723 return; 724 } 725 726 pm_data = (const struct exynos_pm_data *) match->data; 727 728 /* All wakeup disable */ 729 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 730 tmp |= pm_data->wake_disable_mask; 731 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 732 733 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; 734 exynos_pm_syscore_ops.resume = pm_data->pm_resume; 735 736 register_syscore_ops(&exynos_pm_syscore_ops); 737 suspend_set_ops(&exynos_suspend_ops); 738 } 739