xref: /openbmc/linux/arch/arm/mach-exynos/suspend.c (revision ba61bb17) 
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
4 //		http://www.samsung.com
5 //
6 // EXYNOS - Suspend support
7 //
8 // Based on arch/arm/mach-s3c2410/pm.c
9 // Copyright (c) 2006 Simtec Electronics
10 //	Ben Dooks <ben@simtec.co.uk>
11 
12 #include <linux/init.h>
13 #include <linux/suspend.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_address.h>
21 #include <linux/err.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/soc/samsung/exynos-pmu.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
25 
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include <asm/firmware.h>
29 #include <asm/mcpm.h>
30 #include <asm/smp_scu.h>
31 #include <asm/suspend.h>
32 
33 #include <plat/pm-common.h>
34 
35 #include "common.h"
36 
37 #define REG_TABLE_END (-1U)
38 
39 #define EXYNOS5420_CPU_STATE	0x28
40 
41 /**
42  * struct exynos_wkup_irq - PMU IRQ to mask mapping
43  * @hwirq: Hardware IRQ signal of the PMU
44  * @mask: Mask in PMU wake-up mask register
45  */
46 struct exynos_wkup_irq {
47 	unsigned int hwirq;
48 	u32 mask;
49 };
50 
51 struct exynos_pm_data {
52 	const struct exynos_wkup_irq *wkup_irq;
53 	unsigned int wake_disable_mask;
54 
55 	void (*pm_prepare)(void);
56 	void (*pm_resume_prepare)(void);
57 	void (*pm_resume)(void);
58 	int (*pm_suspend)(void);
59 	int (*cpu_suspend)(unsigned long);
60 };
61 
62 static const struct exynos_pm_data *pm_data __ro_after_init;
63 
64 static int exynos5420_cpu_state;
65 static unsigned int exynos_pmu_spare3;
66 
67 /*
68  * GIC wake-up support
69  */
70 
71 static u32 exynos_irqwake_intmask = 0xffffffff;
72 
73 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
74 	{ 73, BIT(1) }, /* RTC alarm */
75 	{ 74, BIT(2) }, /* RTC tick */
76 	{ /* sentinel */ },
77 };
78 
79 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
80 	{ 44, BIT(1) }, /* RTC alarm */
81 	{ 45, BIT(2) }, /* RTC tick */
82 	{ /* sentinel */ },
83 };
84 
85 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
86 	{ 43, BIT(1) }, /* RTC alarm */
87 	{ 44, BIT(2) }, /* RTC tick */
88 	{ /* sentinel */ },
89 };
90 
91 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
92 {
93 	const struct exynos_wkup_irq *wkup_irq;
94 
95 	if (!pm_data->wkup_irq)
96 		return -ENOENT;
97 	wkup_irq = pm_data->wkup_irq;
98 
99 	while (wkup_irq->mask) {
100 		if (wkup_irq->hwirq == data->hwirq) {
101 			if (!state)
102 				exynos_irqwake_intmask |= wkup_irq->mask;
103 			else
104 				exynos_irqwake_intmask &= ~wkup_irq->mask;
105 			return 0;
106 		}
107 		++wkup_irq;
108 	}
109 
110 	return -ENOENT;
111 }
112 
113 static struct irq_chip exynos_pmu_chip = {
114 	.name			= "PMU",
115 	.irq_eoi		= irq_chip_eoi_parent,
116 	.irq_mask		= irq_chip_mask_parent,
117 	.irq_unmask		= irq_chip_unmask_parent,
118 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
119 	.irq_set_wake		= exynos_irq_set_wake,
120 #ifdef CONFIG_SMP
121 	.irq_set_affinity	= irq_chip_set_affinity_parent,
122 #endif
123 };
124 
125 static int exynos_pmu_domain_translate(struct irq_domain *d,
126 				       struct irq_fwspec *fwspec,
127 				       unsigned long *hwirq,
128 				       unsigned int *type)
129 {
130 	if (is_of_node(fwspec->fwnode)) {
131 		if (fwspec->param_count != 3)
132 			return -EINVAL;
133 
134 		/* No PPI should point to this domain */
135 		if (fwspec->param[0] != 0)
136 			return -EINVAL;
137 
138 		*hwirq = fwspec->param[1];
139 		*type = fwspec->param[2];
140 		return 0;
141 	}
142 
143 	return -EINVAL;
144 }
145 
146 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
147 				   unsigned int virq,
148 				   unsigned int nr_irqs, void *data)
149 {
150 	struct irq_fwspec *fwspec = data;
151 	struct irq_fwspec parent_fwspec;
152 	irq_hw_number_t hwirq;
153 	int i;
154 
155 	if (fwspec->param_count != 3)
156 		return -EINVAL;	/* Not GIC compliant */
157 	if (fwspec->param[0] != 0)
158 		return -EINVAL;	/* No PPI should point to this domain */
159 
160 	hwirq = fwspec->param[1];
161 
162 	for (i = 0; i < nr_irqs; i++)
163 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
164 					      &exynos_pmu_chip, NULL);
165 
166 	parent_fwspec = *fwspec;
167 	parent_fwspec.fwnode = domain->parent->fwnode;
168 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
169 					    &parent_fwspec);
170 }
171 
172 static const struct irq_domain_ops exynos_pmu_domain_ops = {
173 	.translate	= exynos_pmu_domain_translate,
174 	.alloc		= exynos_pmu_domain_alloc,
175 	.free		= irq_domain_free_irqs_common,
176 };
177 
178 static int __init exynos_pmu_irq_init(struct device_node *node,
179 				      struct device_node *parent)
180 {
181 	struct irq_domain *parent_domain, *domain;
182 
183 	if (!parent) {
184 		pr_err("%pOF: no parent, giving up\n", node);
185 		return -ENODEV;
186 	}
187 
188 	parent_domain = irq_find_host(parent);
189 	if (!parent_domain) {
190 		pr_err("%pOF: unable to obtain parent domain\n", node);
191 		return -ENXIO;
192 	}
193 
194 	pmu_base_addr = of_iomap(node, 0);
195 
196 	if (!pmu_base_addr) {
197 		pr_err("%pOF: failed to find exynos pmu register\n", node);
198 		return -ENOMEM;
199 	}
200 
201 	domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
202 					  node, &exynos_pmu_domain_ops,
203 					  NULL);
204 	if (!domain) {
205 		iounmap(pmu_base_addr);
206 		return -ENOMEM;
207 	}
208 
209 	/*
210 	 * Clear the OF_POPULATED flag set in of_irq_init so that
211 	 * later the Exynos PMU platform device won't be skipped.
212 	 */
213 	of_node_clear_flag(node, OF_POPULATED);
214 
215 	return 0;
216 }
217 
218 #define EXYNOS_PMU_IRQ(symbol, name)	IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
219 
220 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
221 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
222 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
223 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
224 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
225 
226 static int exynos_cpu_do_idle(void)
227 {
228 	/* issue the standby signal into the pm unit. */
229 	cpu_do_idle();
230 
231 	pr_info("Failed to suspend the system\n");
232 	return 1; /* Aborting suspend */
233 }
234 static void exynos_flush_cache_all(void)
235 {
236 	flush_cache_all();
237 	outer_flush_all();
238 }
239 
240 static int exynos_cpu_suspend(unsigned long arg)
241 {
242 	exynos_flush_cache_all();
243 	return exynos_cpu_do_idle();
244 }
245 
246 static int exynos3250_cpu_suspend(unsigned long arg)
247 {
248 	flush_cache_all();
249 	return exynos_cpu_do_idle();
250 }
251 
252 static int exynos5420_cpu_suspend(unsigned long arg)
253 {
254 	/* MCPM works with HW CPU identifiers */
255 	unsigned int mpidr = read_cpuid_mpidr();
256 	unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
257 	unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
258 
259 	writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
260 
261 	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
262 		mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
263 		mcpm_cpu_suspend();
264 	}
265 
266 	pr_info("Failed to suspend the system\n");
267 
268 	/* return value != 0 means failure */
269 	return 1;
270 }
271 
272 static void exynos_pm_set_wakeup_mask(void)
273 {
274 	/* Set wake-up mask registers */
275 	pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
276 	pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
277 }
278 
279 static void exynos_pm_enter_sleep_mode(void)
280 {
281 	/* Set value of power down register for sleep mode */
282 	exynos_sys_powerdown_conf(SYS_SLEEP);
283 	pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
284 }
285 
286 static void exynos_pm_prepare(void)
287 {
288 	exynos_set_delayed_reset_assertion(false);
289 
290 	/* Set wake-up mask registers */
291 	exynos_pm_set_wakeup_mask();
292 
293 	exynos_pm_enter_sleep_mode();
294 
295 	/* ensure at least INFORM0 has the resume address */
296 	pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
297 }
298 
299 static void exynos3250_pm_prepare(void)
300 {
301 	unsigned int tmp;
302 
303 	/* Set wake-up mask registers */
304 	exynos_pm_set_wakeup_mask();
305 
306 	tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
307 	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
308 	pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
309 
310 	exynos_pm_enter_sleep_mode();
311 
312 	/* ensure at least INFORM0 has the resume address */
313 	pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
314 }
315 
316 static void exynos5420_pm_prepare(void)
317 {
318 	unsigned int tmp;
319 
320 	/* Set wake-up mask registers */
321 	exynos_pm_set_wakeup_mask();
322 
323 	exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
324 	/*
325 	 * The cpu state needs to be saved and restored so that the
326 	 * secondary CPUs will enter low power start. Though the U-Boot
327 	 * is setting the cpu state with low power flag, the kernel
328 	 * needs to restore it back in case, the primary cpu fails to
329 	 * suspend for any reason.
330 	 */
331 	exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
332 					     EXYNOS5420_CPU_STATE);
333 
334 	exynos_pm_enter_sleep_mode();
335 
336 	/* ensure at least INFORM0 has the resume address */
337 	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
338 		pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
339 
340 	tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
341 	tmp &= ~EXYNOS_L2_USE_RETENTION;
342 	pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
343 
344 	tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
345 	tmp |= EXYNOS5420_UFS;
346 	pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
347 
348 	tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
349 	tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
350 	pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
351 
352 	tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
353 	tmp |= EXYNOS5420_EMULATION;
354 	pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
355 
356 	tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
357 	tmp |= EXYNOS5420_EMULATION;
358 	pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
359 }
360 
361 
362 static int exynos_pm_suspend(void)
363 {
364 	exynos_pm_central_suspend();
365 
366 	/* Setting SEQ_OPTION register */
367 	pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
368 		       S5P_CENTRAL_SEQ_OPTION);
369 
370 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
371 		exynos_cpu_save_register();
372 
373 	return 0;
374 }
375 
376 static int exynos5420_pm_suspend(void)
377 {
378 	u32 this_cluster;
379 
380 	exynos_pm_central_suspend();
381 
382 	/* Setting SEQ_OPTION register */
383 
384 	this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
385 	if (!this_cluster)
386 		pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
387 				S5P_CENTRAL_SEQ_OPTION);
388 	else
389 		pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
390 				S5P_CENTRAL_SEQ_OPTION);
391 	return 0;
392 }
393 
394 static void exynos_pm_resume(void)
395 {
396 	u32 cpuid = read_cpuid_part();
397 
398 	if (exynos_pm_central_resume())
399 		goto early_wakeup;
400 
401 	if (cpuid == ARM_CPU_PART_CORTEX_A9)
402 		exynos_scu_enable();
403 
404 	if (call_firmware_op(resume) == -ENOSYS
405 	    && cpuid == ARM_CPU_PART_CORTEX_A9)
406 		exynos_cpu_restore_register();
407 
408 early_wakeup:
409 
410 	/* Clear SLEEP mode set in INFORM1 */
411 	pmu_raw_writel(0x0, S5P_INFORM1);
412 	exynos_set_delayed_reset_assertion(true);
413 }
414 
415 static void exynos3250_pm_resume(void)
416 {
417 	u32 cpuid = read_cpuid_part();
418 
419 	if (exynos_pm_central_resume())
420 		goto early_wakeup;
421 
422 	pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
423 
424 	if (call_firmware_op(resume) == -ENOSYS
425 	    && cpuid == ARM_CPU_PART_CORTEX_A9)
426 		exynos_cpu_restore_register();
427 
428 early_wakeup:
429 
430 	/* Clear SLEEP mode set in INFORM1 */
431 	pmu_raw_writel(0x0, S5P_INFORM1);
432 }
433 
434 static void exynos5420_prepare_pm_resume(void)
435 {
436 	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
437 		WARN_ON(mcpm_cpu_powered_up());
438 }
439 
440 static void exynos5420_pm_resume(void)
441 {
442 	unsigned long tmp;
443 
444 	/* Restore the CPU0 low power state register */
445 	tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
446 	pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
447 		       EXYNOS5_ARM_CORE0_SYS_PWR_REG);
448 
449 	/* Restore the sysram cpu state register */
450 	writel_relaxed(exynos5420_cpu_state,
451 		       sysram_base_addr + EXYNOS5420_CPU_STATE);
452 
453 	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
454 			S5P_CENTRAL_SEQ_OPTION);
455 
456 	if (exynos_pm_central_resume())
457 		goto early_wakeup;
458 
459 	pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
460 
461 early_wakeup:
462 
463 	tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
464 	tmp &= ~EXYNOS5420_UFS;
465 	pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
466 
467 	tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
468 	tmp &= ~EXYNOS5420_EMULATION;
469 	pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
470 
471 	tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
472 	tmp &= ~EXYNOS5420_EMULATION;
473 	pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
474 
475 	/* Clear SLEEP mode set in INFORM1 */
476 	pmu_raw_writel(0x0, S5P_INFORM1);
477 }
478 
479 /*
480  * Suspend Ops
481  */
482 
483 static int exynos_suspend_enter(suspend_state_t state)
484 {
485 	int ret;
486 
487 	s3c_pm_debug_init();
488 
489 	S3C_PMDBG("%s: suspending the system...\n", __func__);
490 
491 	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
492 			exynos_irqwake_intmask, exynos_get_eint_wake_mask());
493 
494 	if (exynos_irqwake_intmask == -1U
495 	    && exynos_get_eint_wake_mask() == -1U) {
496 		pr_err("%s: No wake-up sources!\n", __func__);
497 		pr_err("%s: Aborting sleep\n", __func__);
498 		return -EINVAL;
499 	}
500 
501 	s3c_pm_save_uarts();
502 	if (pm_data->pm_prepare)
503 		pm_data->pm_prepare();
504 	flush_cache_all();
505 	s3c_pm_check_store();
506 
507 	ret = call_firmware_op(suspend);
508 	if (ret == -ENOSYS)
509 		ret = cpu_suspend(0, pm_data->cpu_suspend);
510 	if (ret)
511 		return ret;
512 
513 	if (pm_data->pm_resume_prepare)
514 		pm_data->pm_resume_prepare();
515 	s3c_pm_restore_uarts();
516 
517 	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
518 			pmu_raw_readl(S5P_WAKEUP_STAT));
519 
520 	s3c_pm_check_restore();
521 
522 	S3C_PMDBG("%s: resuming the system...\n", __func__);
523 
524 	return 0;
525 }
526 
527 static int exynos_suspend_prepare(void)
528 {
529 	int ret;
530 
531 	/*
532 	 * REVISIT: It would be better if struct platform_suspend_ops
533 	 * .prepare handler get the suspend_state_t as a parameter to
534 	 * avoid hard-coding the suspend to mem state. It's safe to do
535 	 * it now only because the suspend_valid_only_mem function is
536 	 * used as the .valid callback used to check if a given state
537 	 * is supported by the platform anyways.
538 	 */
539 	ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
540 	if (ret) {
541 		pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
542 		return ret;
543 	}
544 
545 	s3c_pm_check_prepare();
546 
547 	return 0;
548 }
549 
550 static void exynos_suspend_finish(void)
551 {
552 	int ret;
553 
554 	s3c_pm_check_cleanup();
555 
556 	ret = regulator_suspend_finish();
557 	if (ret)
558 		pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
559 }
560 
561 static const struct platform_suspend_ops exynos_suspend_ops = {
562 	.enter		= exynos_suspend_enter,
563 	.prepare	= exynos_suspend_prepare,
564 	.finish		= exynos_suspend_finish,
565 	.valid		= suspend_valid_only_mem,
566 };
567 
568 static const struct exynos_pm_data exynos3250_pm_data = {
569 	.wkup_irq	= exynos3250_wkup_irq,
570 	.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
571 	.pm_suspend	= exynos_pm_suspend,
572 	.pm_resume	= exynos3250_pm_resume,
573 	.pm_prepare	= exynos3250_pm_prepare,
574 	.cpu_suspend	= exynos3250_cpu_suspend,
575 };
576 
577 static const struct exynos_pm_data exynos4_pm_data = {
578 	.wkup_irq	= exynos4_wkup_irq,
579 	.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
580 	.pm_suspend	= exynos_pm_suspend,
581 	.pm_resume	= exynos_pm_resume,
582 	.pm_prepare	= exynos_pm_prepare,
583 	.cpu_suspend	= exynos_cpu_suspend,
584 };
585 
586 static const struct exynos_pm_data exynos5250_pm_data = {
587 	.wkup_irq	= exynos5250_wkup_irq,
588 	.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
589 	.pm_suspend	= exynos_pm_suspend,
590 	.pm_resume	= exynos_pm_resume,
591 	.pm_prepare	= exynos_pm_prepare,
592 	.cpu_suspend	= exynos_cpu_suspend,
593 };
594 
595 static const struct exynos_pm_data exynos5420_pm_data = {
596 	.wkup_irq	= exynos5250_wkup_irq,
597 	.wake_disable_mask = (0x7F << 7) | (0x1F << 1),
598 	.pm_resume_prepare = exynos5420_prepare_pm_resume,
599 	.pm_resume	= exynos5420_pm_resume,
600 	.pm_suspend	= exynos5420_pm_suspend,
601 	.pm_prepare	= exynos5420_pm_prepare,
602 	.cpu_suspend	= exynos5420_cpu_suspend,
603 };
604 
605 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
606 	{
607 		.compatible = "samsung,exynos3250-pmu",
608 		.data = &exynos3250_pm_data,
609 	}, {
610 		.compatible = "samsung,exynos4210-pmu",
611 		.data = &exynos4_pm_data,
612 	}, {
613 		.compatible = "samsung,exynos4412-pmu",
614 		.data = &exynos4_pm_data,
615 	}, {
616 		.compatible = "samsung,exynos5250-pmu",
617 		.data = &exynos5250_pm_data,
618 	}, {
619 		.compatible = "samsung,exynos5420-pmu",
620 		.data = &exynos5420_pm_data,
621 	},
622 	{ /*sentinel*/ },
623 };
624 
625 static struct syscore_ops exynos_pm_syscore_ops;
626 
627 void __init exynos_pm_init(void)
628 {
629 	const struct of_device_id *match;
630 	struct device_node *np;
631 	u32 tmp;
632 
633 	np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
634 	if (!np) {
635 		pr_err("Failed to find PMU node\n");
636 		return;
637 	}
638 
639 	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
640 		pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
641 		return;
642 	}
643 
644 	pm_data = (const struct exynos_pm_data *) match->data;
645 
646 	/* All wakeup disable */
647 	tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
648 	tmp |= pm_data->wake_disable_mask;
649 	pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
650 
651 	exynos_pm_syscore_ops.suspend	= pm_data->pm_suspend;
652 	exynos_pm_syscore_ops.resume	= pm_data->pm_resume;
653 
654 	register_syscore_ops(&exynos_pm_syscore_ops);
655 	suspend_set_ops(&exynos_suspend_ops);
656 }
657