1 /* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power Management support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/cpu_pm.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/soc/samsung/exynos-regs-pmu.h> 22 #include <linux/soc/samsung/exynos-pmu.h> 23 24 #include <asm/firmware.h> 25 #include <asm/smp_scu.h> 26 #include <asm/suspend.h> 27 #include <asm/cacheflush.h> 28 29 #include <mach/map.h> 30 31 #include "common.h" 32 33 static inline void __iomem *exynos_boot_vector_addr(void) 34 { 35 if (samsung_rev() == EXYNOS4210_REV_1_1) 36 return pmu_base_addr + S5P_INFORM7; 37 else if (samsung_rev() == EXYNOS4210_REV_1_0) 38 return sysram_base_addr + 0x24; 39 return pmu_base_addr + S5P_INFORM0; 40 } 41 42 static inline void __iomem *exynos_boot_vector_flag(void) 43 { 44 if (samsung_rev() == EXYNOS4210_REV_1_1) 45 return pmu_base_addr + S5P_INFORM6; 46 else if (samsung_rev() == EXYNOS4210_REV_1_0) 47 return sysram_base_addr + 0x20; 48 return pmu_base_addr + S5P_INFORM1; 49 } 50 51 #define S5P_CHECK_AFTR 0xFCBA0D10 52 53 /* For Cortex-A9 Diagnostic and Power control register */ 54 static unsigned int save_arm_register[2]; 55 56 void exynos_cpu_save_register(void) 57 { 58 unsigned long tmp; 59 60 /* Save Power control register */ 61 asm ("mrc p15, 0, %0, c15, c0, 0" 62 : "=r" (tmp) : : "cc"); 63 64 save_arm_register[0] = tmp; 65 66 /* Save Diagnostic register */ 67 asm ("mrc p15, 0, %0, c15, c0, 1" 68 : "=r" (tmp) : : "cc"); 69 70 save_arm_register[1] = tmp; 71 } 72 73 void exynos_cpu_restore_register(void) 74 { 75 unsigned long tmp; 76 77 /* Restore Power control register */ 78 tmp = save_arm_register[0]; 79 80 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 81 : : "r" (tmp) 82 : "cc"); 83 84 /* Restore Diagnostic register */ 85 tmp = save_arm_register[1]; 86 87 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 88 : : "r" (tmp) 89 : "cc"); 90 } 91 92 void exynos_pm_central_suspend(void) 93 { 94 unsigned long tmp; 95 96 /* Setting Central Sequence Register for power down mode */ 97 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 98 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 99 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 100 } 101 102 int exynos_pm_central_resume(void) 103 { 104 unsigned long tmp; 105 106 /* 107 * If PMU failed while entering sleep mode, WFI will be 108 * ignored by PMU and then exiting cpu_do_idle(). 109 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 110 * in this situation. 111 */ 112 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 113 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 114 tmp |= S5P_CENTRAL_LOWPWR_CFG; 115 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 116 /* clear the wakeup state register */ 117 pmu_raw_writel(0x0, S5P_WAKEUP_STAT); 118 /* No need to perform below restore code */ 119 return -1; 120 } 121 122 return 0; 123 } 124 125 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 126 static void exynos_set_wakeupmask(long mask) 127 { 128 pmu_raw_writel(mask, S5P_WAKEUP_MASK); 129 if (soc_is_exynos3250()) 130 pmu_raw_writel(0x0, S5P_WAKEUP_MASK2); 131 } 132 133 static void exynos_cpu_set_boot_vector(long flags) 134 { 135 writel_relaxed(__pa_symbol(exynos_cpu_resume), 136 exynos_boot_vector_addr()); 137 writel_relaxed(flags, exynos_boot_vector_flag()); 138 } 139 140 static int exynos_aftr_finisher(unsigned long flags) 141 { 142 int ret; 143 144 exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e); 145 /* Set value of power down register for aftr mode */ 146 exynos_sys_powerdown_conf(SYS_AFTR); 147 148 ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR); 149 if (ret == -ENOSYS) { 150 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 151 exynos_cpu_save_register(); 152 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); 153 cpu_do_idle(); 154 } 155 156 return 1; 157 } 158 159 void exynos_enter_aftr(void) 160 { 161 unsigned int cpuid = smp_processor_id(); 162 163 cpu_pm_enter(); 164 165 if (soc_is_exynos3250()) 166 exynos_set_boot_flag(cpuid, C2_STATE); 167 168 exynos_pm_central_suspend(); 169 170 if (of_machine_is_compatible("samsung,exynos4412")) { 171 /* Setting SEQ_OPTION register */ 172 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 173 S5P_CENTRAL_SEQ_OPTION); 174 } 175 176 cpu_suspend(0, exynos_aftr_finisher); 177 178 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 179 scu_enable(S5P_VA_SCU); 180 if (call_firmware_op(resume) == -ENOSYS) 181 exynos_cpu_restore_register(); 182 } 183 184 exynos_pm_central_resume(); 185 186 if (soc_is_exynos3250()) 187 exynos_clear_boot_flag(cpuid, C2_STATE); 188 189 cpu_pm_exit(); 190 } 191 192 #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE) 193 static atomic_t cpu1_wakeup = ATOMIC_INIT(0); 194 195 static int exynos_cpu0_enter_aftr(void) 196 { 197 int ret = -1; 198 199 /* 200 * If the other cpu is powered on, we have to power it off, because 201 * the AFTR state won't work otherwise 202 */ 203 if (cpu_online(1)) { 204 /* 205 * We reach a sync point with the coupled idle state, we know 206 * the other cpu will power down itself or will abort the 207 * sequence, let's wait for one of these to happen 208 */ 209 while (exynos_cpu_power_state(1)) { 210 unsigned long boot_addr; 211 212 /* 213 * The other cpu may skip idle and boot back 214 * up again 215 */ 216 if (atomic_read(&cpu1_wakeup)) 217 goto abort; 218 219 /* 220 * The other cpu may bounce through idle and 221 * boot back up again, getting stuck in the 222 * boot rom code 223 */ 224 ret = exynos_get_boot_addr(1, &boot_addr); 225 if (ret) 226 goto fail; 227 ret = -1; 228 if (boot_addr == 0) 229 goto abort; 230 231 cpu_relax(); 232 } 233 } 234 235 exynos_enter_aftr(); 236 ret = 0; 237 238 abort: 239 if (cpu_online(1)) { 240 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume); 241 242 /* 243 * Set the boot vector to something non-zero 244 */ 245 ret = exynos_set_boot_addr(1, boot_addr); 246 if (ret) 247 goto fail; 248 dsb(); 249 250 /* 251 * Turn on cpu1 and wait for it to be on 252 */ 253 exynos_cpu_power_up(1); 254 while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN) 255 cpu_relax(); 256 257 if (soc_is_exynos3250()) { 258 while (!pmu_raw_readl(S5P_PMU_SPARE2) && 259 !atomic_read(&cpu1_wakeup)) 260 cpu_relax(); 261 262 if (!atomic_read(&cpu1_wakeup)) 263 exynos_core_restart(1); 264 } 265 266 while (!atomic_read(&cpu1_wakeup)) { 267 smp_rmb(); 268 269 /* 270 * Poke cpu1 out of the boot rom 271 */ 272 273 ret = exynos_set_boot_addr(1, boot_addr); 274 if (ret) 275 goto fail; 276 277 call_firmware_op(cpu_boot, 1); 278 279 if (soc_is_exynos3250()) 280 dsb_sev(); 281 else 282 arch_send_wakeup_ipi_mask(cpumask_of(1)); 283 } 284 } 285 fail: 286 return ret; 287 } 288 289 static int exynos_wfi_finisher(unsigned long flags) 290 { 291 if (soc_is_exynos3250()) 292 flush_cache_all(); 293 cpu_do_idle(); 294 295 return -1; 296 } 297 298 static int exynos_cpu1_powerdown(void) 299 { 300 int ret = -1; 301 302 /* 303 * Idle sequence for cpu1 304 */ 305 if (cpu_pm_enter()) 306 goto cpu1_aborted; 307 308 /* 309 * Turn off cpu 1 310 */ 311 exynos_cpu_power_down(1); 312 313 if (soc_is_exynos3250()) 314 pmu_raw_writel(0, S5P_PMU_SPARE2); 315 316 ret = cpu_suspend(0, exynos_wfi_finisher); 317 318 cpu_pm_exit(); 319 320 cpu1_aborted: 321 dsb(); 322 /* 323 * Notify cpu 0 that cpu 1 is awake 324 */ 325 atomic_set(&cpu1_wakeup, 1); 326 327 return ret; 328 } 329 330 static void exynos_pre_enter_aftr(void) 331 { 332 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume); 333 334 (void)exynos_set_boot_addr(1, boot_addr); 335 } 336 337 static void exynos_post_enter_aftr(void) 338 { 339 atomic_set(&cpu1_wakeup, 0); 340 } 341 342 struct cpuidle_exynos_data cpuidle_coupled_exynos_data = { 343 .cpu0_enter_aftr = exynos_cpu0_enter_aftr, 344 .cpu1_powerdown = exynos_cpu1_powerdown, 345 .pre_enter_aftr = exynos_pre_enter_aftr, 346 .post_enter_aftr = exynos_post_enter_aftr, 347 }; 348 #endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */ 349