1 /* 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power Management support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/io.h> 20 #include <linux/irqchip/arm-gic.h> 21 #include <linux/err.h> 22 #include <linux/clk.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/hardware/cache-l2x0.h> 26 #include <asm/smp_scu.h> 27 #include <asm/suspend.h> 28 29 #include <plat/cpu.h> 30 #include <plat/pm-common.h> 31 #include <plat/pll.h> 32 #include <plat/regs-srom.h> 33 34 #include <mach/map.h> 35 36 #include "common.h" 37 #include "regs-pmu.h" 38 39 /** 40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping 41 * @hwirq: Hardware IRQ signal of the GIC 42 * @mask: Mask in PMU wake-up mask register 43 */ 44 struct exynos_wkup_irq { 45 unsigned int hwirq; 46 u32 mask; 47 }; 48 49 static struct sleep_save exynos5_sys_save[] = { 50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 51 }; 52 53 static struct sleep_save exynos_core_save[] = { 54 /* SROM side */ 55 SAVE_ITEM(S5P_SROM_BW), 56 SAVE_ITEM(S5P_SROM_BC0), 57 SAVE_ITEM(S5P_SROM_BC1), 58 SAVE_ITEM(S5P_SROM_BC2), 59 SAVE_ITEM(S5P_SROM_BC3), 60 }; 61 62 /* 63 * GIC wake-up support 64 */ 65 66 static u32 exynos_irqwake_intmask = 0xffffffff; 67 68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 69 { 76, BIT(1) }, /* RTC alarm */ 70 { 77, BIT(2) }, /* RTC tick */ 71 { /* sentinel */ }, 72 }; 73 74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 75 { 75, BIT(1) }, /* RTC alarm */ 76 { 76, BIT(2) }, /* RTC tick */ 77 { /* sentinel */ }, 78 }; 79 80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 81 { 82 const struct exynos_wkup_irq *wkup_irq; 83 84 if (soc_is_exynos5250()) 85 wkup_irq = exynos5250_wkup_irq; 86 else 87 wkup_irq = exynos4_wkup_irq; 88 89 while (wkup_irq->mask) { 90 if (wkup_irq->hwirq == data->hwirq) { 91 if (!state) 92 exynos_irqwake_intmask |= wkup_irq->mask; 93 else 94 exynos_irqwake_intmask &= ~wkup_irq->mask; 95 return 0; 96 } 97 ++wkup_irq; 98 } 99 100 return -ENOENT; 101 } 102 103 /* For Cortex-A9 Diagnostic and Power control register */ 104 static unsigned int save_arm_register[2]; 105 106 static int exynos_cpu_suspend(unsigned long arg) 107 { 108 #ifdef CONFIG_CACHE_L2X0 109 outer_flush_all(); 110 #endif 111 112 if (soc_is_exynos5250()) 113 flush_cache_all(); 114 115 /* issue the standby signal into the pm unit. */ 116 cpu_do_idle(); 117 118 pr_info("Failed to suspend the system\n"); 119 return 1; /* Aborting suspend */ 120 } 121 122 static void exynos_pm_prepare(void) 123 { 124 unsigned int tmp; 125 126 /* Set wake-up mask registers */ 127 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 128 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 129 130 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 131 132 if (soc_is_exynos5250()) { 133 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 134 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 135 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 136 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 137 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 138 } 139 140 /* Set value of power down register for sleep mode */ 141 142 exynos_sys_powerdown_conf(SYS_SLEEP); 143 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 144 145 /* ensure at least INFORM0 has the resume address */ 146 147 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 148 } 149 150 static int exynos_pm_suspend(void) 151 { 152 unsigned long tmp; 153 154 /* Setting Central Sequence Register for power down mode */ 155 156 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 157 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 158 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 159 160 /* Setting SEQ_OPTION register */ 161 162 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 163 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 164 165 if (!soc_is_exynos5250()) { 166 /* Save Power control register */ 167 asm ("mrc p15, 0, %0, c15, c0, 0" 168 : "=r" (tmp) : : "cc"); 169 save_arm_register[0] = tmp; 170 171 /* Save Diagnostic register */ 172 asm ("mrc p15, 0, %0, c15, c0, 1" 173 : "=r" (tmp) : : "cc"); 174 save_arm_register[1] = tmp; 175 } 176 177 return 0; 178 } 179 180 static void exynos_pm_resume(void) 181 { 182 unsigned long tmp; 183 184 /* 185 * If PMU failed while entering sleep mode, WFI will be 186 * ignored by PMU and then exiting cpu_do_idle(). 187 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 188 * in this situation. 189 */ 190 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 191 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 192 tmp |= S5P_CENTRAL_LOWPWR_CFG; 193 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 194 /* clear the wakeup state register */ 195 __raw_writel(0x0, S5P_WAKEUP_STAT); 196 /* No need to perform below restore code */ 197 goto early_wakeup; 198 } 199 if (!soc_is_exynos5250()) { 200 /* Restore Power control register */ 201 tmp = save_arm_register[0]; 202 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 203 : : "r" (tmp) 204 : "cc"); 205 206 /* Restore Diagnostic register */ 207 tmp = save_arm_register[1]; 208 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 209 : : "r" (tmp) 210 : "cc"); 211 } 212 213 /* For release retention */ 214 215 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 216 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 217 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 218 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 219 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 220 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 221 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 222 223 if (soc_is_exynos5250()) 224 s3c_pm_do_restore(exynos5_sys_save, 225 ARRAY_SIZE(exynos5_sys_save)); 226 227 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 228 229 if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250()) 230 scu_enable(S5P_VA_SCU); 231 232 early_wakeup: 233 234 /* Clear SLEEP mode set in INFORM1 */ 235 __raw_writel(0x0, S5P_INFORM1); 236 237 return; 238 } 239 240 static struct syscore_ops exynos_pm_syscore_ops = { 241 .suspend = exynos_pm_suspend, 242 .resume = exynos_pm_resume, 243 }; 244 245 /* 246 * Suspend Ops 247 */ 248 249 static int exynos_suspend_enter(suspend_state_t state) 250 { 251 int ret; 252 253 s3c_pm_debug_init(); 254 255 S3C_PMDBG("%s: suspending the system...\n", __func__); 256 257 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 258 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 259 260 if (exynos_irqwake_intmask == -1U 261 && exynos_get_eint_wake_mask() == -1U) { 262 pr_err("%s: No wake-up sources!\n", __func__); 263 pr_err("%s: Aborting sleep\n", __func__); 264 return -EINVAL; 265 } 266 267 s3c_pm_save_uarts(); 268 exynos_pm_prepare(); 269 flush_cache_all(); 270 s3c_pm_check_store(); 271 272 ret = cpu_suspend(0, exynos_cpu_suspend); 273 if (ret) 274 return ret; 275 276 s3c_pm_restore_uarts(); 277 278 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 279 __raw_readl(S5P_WAKEUP_STAT)); 280 281 s3c_pm_check_restore(); 282 283 S3C_PMDBG("%s: resuming the system...\n", __func__); 284 285 return 0; 286 } 287 288 static int exynos_suspend_prepare(void) 289 { 290 s3c_pm_check_prepare(); 291 292 return 0; 293 } 294 295 static void exynos_suspend_finish(void) 296 { 297 s3c_pm_check_cleanup(); 298 } 299 300 static const struct platform_suspend_ops exynos_suspend_ops = { 301 .enter = exynos_suspend_enter, 302 .prepare = exynos_suspend_prepare, 303 .finish = exynos_suspend_finish, 304 .valid = suspend_valid_only_mem, 305 }; 306 307 void __init exynos_pm_init(void) 308 { 309 u32 tmp; 310 311 /* Platform-specific GIC callback */ 312 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 313 314 /* All wakeup disable */ 315 tmp = __raw_readl(S5P_WAKEUP_MASK); 316 tmp |= ((0xFF << 8) | (0x1F << 1)); 317 __raw_writel(tmp, S5P_WAKEUP_MASK); 318 319 register_syscore_ops(&exynos_pm_syscore_ops); 320 suspend_set_ops(&exynos_suspend_ops); 321 } 322