1 /* 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power Management support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/io.h> 21 #include <linux/irqchip/arm-gic.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/hardware/cache-l2x0.h> 27 #include <asm/smp_scu.h> 28 #include <asm/suspend.h> 29 30 #include <plat/pm-common.h> 31 #include <plat/regs-srom.h> 32 33 #include <mach/map.h> 34 35 #include "common.h" 36 #include "regs-pmu.h" 37 #include "regs-sys.h" 38 39 /** 40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping 41 * @hwirq: Hardware IRQ signal of the GIC 42 * @mask: Mask in PMU wake-up mask register 43 */ 44 struct exynos_wkup_irq { 45 unsigned int hwirq; 46 u32 mask; 47 }; 48 49 static struct sleep_save exynos5_sys_save[] = { 50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 51 }; 52 53 static struct sleep_save exynos_core_save[] = { 54 /* SROM side */ 55 SAVE_ITEM(S5P_SROM_BW), 56 SAVE_ITEM(S5P_SROM_BC0), 57 SAVE_ITEM(S5P_SROM_BC1), 58 SAVE_ITEM(S5P_SROM_BC2), 59 SAVE_ITEM(S5P_SROM_BC3), 60 }; 61 62 /* 63 * GIC wake-up support 64 */ 65 66 static u32 exynos_irqwake_intmask = 0xffffffff; 67 68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 69 { 76, BIT(1) }, /* RTC alarm */ 70 { 77, BIT(2) }, /* RTC tick */ 71 { /* sentinel */ }, 72 }; 73 74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 75 { 75, BIT(1) }, /* RTC alarm */ 76 { 76, BIT(2) }, /* RTC tick */ 77 { /* sentinel */ }, 78 }; 79 80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 81 { 82 const struct exynos_wkup_irq *wkup_irq; 83 84 if (soc_is_exynos5250()) 85 wkup_irq = exynos5250_wkup_irq; 86 else 87 wkup_irq = exynos4_wkup_irq; 88 89 while (wkup_irq->mask) { 90 if (wkup_irq->hwirq == data->hwirq) { 91 if (!state) 92 exynos_irqwake_intmask |= wkup_irq->mask; 93 else 94 exynos_irqwake_intmask &= ~wkup_irq->mask; 95 return 0; 96 } 97 ++wkup_irq; 98 } 99 100 return -ENOENT; 101 } 102 103 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 104 pmu_base_addr + S5P_INFORM7 : \ 105 (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 106 (sysram_base_addr + 0x24) : \ 107 pmu_base_addr + S5P_INFORM0)) 108 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 109 pmu_base_addr + S5P_INFORM6 : \ 110 (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 111 (sysram_base_addr + 0x20) : \ 112 pmu_base_addr + S5P_INFORM1)) 113 114 #define S5P_CHECK_AFTR 0xFCBA0D10 115 #define S5P_CHECK_SLEEP 0x00000BAD 116 117 /* For Cortex-A9 Diagnostic and Power control register */ 118 static unsigned int save_arm_register[2]; 119 120 static void exynos_cpu_save_register(void) 121 { 122 unsigned long tmp; 123 124 /* Save Power control register */ 125 asm ("mrc p15, 0, %0, c15, c0, 0" 126 : "=r" (tmp) : : "cc"); 127 128 save_arm_register[0] = tmp; 129 130 /* Save Diagnostic register */ 131 asm ("mrc p15, 0, %0, c15, c0, 1" 132 : "=r" (tmp) : : "cc"); 133 134 save_arm_register[1] = tmp; 135 } 136 137 static void exynos_cpu_restore_register(void) 138 { 139 unsigned long tmp; 140 141 /* Restore Power control register */ 142 tmp = save_arm_register[0]; 143 144 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 145 : : "r" (tmp) 146 : "cc"); 147 148 /* Restore Diagnostic register */ 149 tmp = save_arm_register[1]; 150 151 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 152 : : "r" (tmp) 153 : "cc"); 154 } 155 156 static void exynos_pm_central_suspend(void) 157 { 158 unsigned long tmp; 159 160 /* Setting Central Sequence Register for power down mode */ 161 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 162 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 163 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 164 } 165 166 static int exynos_pm_central_resume(void) 167 { 168 unsigned long tmp; 169 170 /* 171 * If PMU failed while entering sleep mode, WFI will be 172 * ignored by PMU and then exiting cpu_do_idle(). 173 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 174 * in this situation. 175 */ 176 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 177 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 178 tmp |= S5P_CENTRAL_LOWPWR_CFG; 179 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 180 /* clear the wakeup state register */ 181 pmu_raw_writel(0x0, S5P_WAKEUP_STAT); 182 /* No need to perform below restore code */ 183 return -1; 184 } 185 186 return 0; 187 } 188 189 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 190 static void exynos_set_wakeupmask(long mask) 191 { 192 pmu_raw_writel(mask, S5P_WAKEUP_MASK); 193 } 194 195 static void exynos_cpu_set_boot_vector(long flags) 196 { 197 __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR); 198 __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG); 199 } 200 201 static int exynos_aftr_finisher(unsigned long flags) 202 { 203 exynos_set_wakeupmask(0x0000ff3e); 204 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); 205 /* Set value of power down register for aftr mode */ 206 exynos_sys_powerdown_conf(SYS_AFTR); 207 cpu_do_idle(); 208 209 return 1; 210 } 211 212 void exynos_enter_aftr(void) 213 { 214 cpu_pm_enter(); 215 216 exynos_pm_central_suspend(); 217 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 218 exynos_cpu_save_register(); 219 220 cpu_suspend(0, exynos_aftr_finisher); 221 222 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 223 scu_enable(S5P_VA_SCU); 224 exynos_cpu_restore_register(); 225 } 226 227 exynos_pm_central_resume(); 228 229 cpu_pm_exit(); 230 } 231 232 static int exynos_cpu_suspend(unsigned long arg) 233 { 234 #ifdef CONFIG_CACHE_L2X0 235 outer_flush_all(); 236 #endif 237 238 if (soc_is_exynos5250()) 239 flush_cache_all(); 240 241 /* issue the standby signal into the pm unit. */ 242 cpu_do_idle(); 243 244 pr_info("Failed to suspend the system\n"); 245 return 1; /* Aborting suspend */ 246 } 247 248 static void exynos_pm_prepare(void) 249 { 250 unsigned int tmp; 251 252 /* Set wake-up mask registers */ 253 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 254 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 255 256 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 257 258 if (soc_is_exynos5250()) { 259 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 260 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 261 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION); 262 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 263 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 264 } 265 266 /* Set value of power down register for sleep mode */ 267 268 exynos_sys_powerdown_conf(SYS_SLEEP); 269 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 270 271 /* ensure at least INFORM0 has the resume address */ 272 273 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 274 } 275 276 static int exynos_pm_suspend(void) 277 { 278 unsigned long tmp; 279 280 exynos_pm_central_suspend(); 281 282 /* Setting SEQ_OPTION register */ 283 284 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 285 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 286 287 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 288 exynos_cpu_save_register(); 289 290 return 0; 291 } 292 293 static void exynos_pm_resume(void) 294 { 295 if (exynos_pm_central_resume()) 296 goto early_wakeup; 297 298 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 299 exynos_cpu_restore_register(); 300 301 /* For release retention */ 302 303 pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 304 pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 305 pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 306 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 307 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 308 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 309 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 310 311 if (soc_is_exynos5250()) 312 s3c_pm_do_restore(exynos5_sys_save, 313 ARRAY_SIZE(exynos5_sys_save)); 314 315 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 316 317 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 318 scu_enable(S5P_VA_SCU); 319 320 early_wakeup: 321 322 /* Clear SLEEP mode set in INFORM1 */ 323 pmu_raw_writel(0x0, S5P_INFORM1); 324 325 return; 326 } 327 328 static struct syscore_ops exynos_pm_syscore_ops = { 329 .suspend = exynos_pm_suspend, 330 .resume = exynos_pm_resume, 331 }; 332 333 /* 334 * Suspend Ops 335 */ 336 337 static int exynos_suspend_enter(suspend_state_t state) 338 { 339 int ret; 340 341 s3c_pm_debug_init(); 342 343 S3C_PMDBG("%s: suspending the system...\n", __func__); 344 345 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 346 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 347 348 if (exynos_irqwake_intmask == -1U 349 && exynos_get_eint_wake_mask() == -1U) { 350 pr_err("%s: No wake-up sources!\n", __func__); 351 pr_err("%s: Aborting sleep\n", __func__); 352 return -EINVAL; 353 } 354 355 s3c_pm_save_uarts(); 356 exynos_pm_prepare(); 357 flush_cache_all(); 358 s3c_pm_check_store(); 359 360 ret = cpu_suspend(0, exynos_cpu_suspend); 361 if (ret) 362 return ret; 363 364 s3c_pm_restore_uarts(); 365 366 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 367 pmu_raw_readl(S5P_WAKEUP_STAT)); 368 369 s3c_pm_check_restore(); 370 371 S3C_PMDBG("%s: resuming the system...\n", __func__); 372 373 return 0; 374 } 375 376 static int exynos_suspend_prepare(void) 377 { 378 s3c_pm_check_prepare(); 379 380 return 0; 381 } 382 383 static void exynos_suspend_finish(void) 384 { 385 s3c_pm_check_cleanup(); 386 } 387 388 static const struct platform_suspend_ops exynos_suspend_ops = { 389 .enter = exynos_suspend_enter, 390 .prepare = exynos_suspend_prepare, 391 .finish = exynos_suspend_finish, 392 .valid = suspend_valid_only_mem, 393 }; 394 395 void __init exynos_pm_init(void) 396 { 397 u32 tmp; 398 399 /* Platform-specific GIC callback */ 400 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 401 402 /* All wakeup disable */ 403 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 404 tmp |= ((0xFF << 8) | (0x1F << 1)); 405 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 406 407 register_syscore_ops(&exynos_pm_syscore_ops); 408 suspend_set_ops(&exynos_suspend_ops); 409 } 410