1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 4 // http://www.samsung.com 5 // 6 // EXYNOS - Power Management support 7 // 8 // Based on arch/arm/mach-s3c2410/pm.c 9 // Copyright (c) 2006 Simtec Electronics 10 // Ben Dooks <ben@simtec.co.uk> 11 12 #include <linux/init.h> 13 #include <linux/suspend.h> 14 #include <linux/cpu_pm.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 #include <linux/soc/samsung/exynos-pmu.h> 19 20 #include <asm/firmware.h> 21 #include <asm/smp_scu.h> 22 #include <asm/suspend.h> 23 #include <asm/cacheflush.h> 24 25 #include <mach/map.h> 26 27 #include "common.h" 28 29 static inline void __iomem *exynos_boot_vector_addr(void) 30 { 31 if (samsung_rev() == EXYNOS4210_REV_1_1) 32 return pmu_base_addr + S5P_INFORM7; 33 else if (samsung_rev() == EXYNOS4210_REV_1_0) 34 return sysram_base_addr + 0x24; 35 return pmu_base_addr + S5P_INFORM0; 36 } 37 38 static inline void __iomem *exynos_boot_vector_flag(void) 39 { 40 if (samsung_rev() == EXYNOS4210_REV_1_1) 41 return pmu_base_addr + S5P_INFORM6; 42 else if (samsung_rev() == EXYNOS4210_REV_1_0) 43 return sysram_base_addr + 0x20; 44 return pmu_base_addr + S5P_INFORM1; 45 } 46 47 #define S5P_CHECK_AFTR 0xFCBA0D10 48 49 /* For Cortex-A9 Diagnostic and Power control register */ 50 static unsigned int save_arm_register[2]; 51 52 void exynos_cpu_save_register(void) 53 { 54 unsigned long tmp; 55 56 /* Save Power control register */ 57 asm ("mrc p15, 0, %0, c15, c0, 0" 58 : "=r" (tmp) : : "cc"); 59 60 save_arm_register[0] = tmp; 61 62 /* Save Diagnostic register */ 63 asm ("mrc p15, 0, %0, c15, c0, 1" 64 : "=r" (tmp) : : "cc"); 65 66 save_arm_register[1] = tmp; 67 } 68 69 void exynos_cpu_restore_register(void) 70 { 71 unsigned long tmp; 72 73 /* Restore Power control register */ 74 tmp = save_arm_register[0]; 75 76 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 77 : : "r" (tmp) 78 : "cc"); 79 80 /* Restore Diagnostic register */ 81 tmp = save_arm_register[1]; 82 83 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 84 : : "r" (tmp) 85 : "cc"); 86 } 87 88 void exynos_pm_central_suspend(void) 89 { 90 unsigned long tmp; 91 92 /* Setting Central Sequence Register for power down mode */ 93 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 94 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 95 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 96 } 97 98 int exynos_pm_central_resume(void) 99 { 100 unsigned long tmp; 101 102 /* 103 * If PMU failed while entering sleep mode, WFI will be 104 * ignored by PMU and then exiting cpu_do_idle(). 105 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 106 * in this situation. 107 */ 108 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 109 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 110 tmp |= S5P_CENTRAL_LOWPWR_CFG; 111 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 112 /* clear the wakeup state register */ 113 pmu_raw_writel(0x0, S5P_WAKEUP_STAT); 114 /* No need to perform below restore code */ 115 return -1; 116 } 117 118 return 0; 119 } 120 121 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 122 static void exynos_set_wakeupmask(long mask) 123 { 124 pmu_raw_writel(mask, S5P_WAKEUP_MASK); 125 if (soc_is_exynos3250()) 126 pmu_raw_writel(0x0, S5P_WAKEUP_MASK2); 127 } 128 129 static void exynos_cpu_set_boot_vector(long flags) 130 { 131 writel_relaxed(__pa_symbol(exynos_cpu_resume), 132 exynos_boot_vector_addr()); 133 writel_relaxed(flags, exynos_boot_vector_flag()); 134 } 135 136 static int exynos_aftr_finisher(unsigned long flags) 137 { 138 int ret; 139 140 exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e); 141 /* Set value of power down register for aftr mode */ 142 exynos_sys_powerdown_conf(SYS_AFTR); 143 144 ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR); 145 if (ret == -ENOSYS) { 146 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 147 exynos_cpu_save_register(); 148 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); 149 cpu_do_idle(); 150 } 151 152 return 1; 153 } 154 155 void exynos_enter_aftr(void) 156 { 157 unsigned int cpuid = smp_processor_id(); 158 159 cpu_pm_enter(); 160 161 if (soc_is_exynos3250()) 162 exynos_set_boot_flag(cpuid, C2_STATE); 163 164 exynos_pm_central_suspend(); 165 166 if (soc_is_exynos4412()) { 167 /* Setting SEQ_OPTION register */ 168 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 169 S5P_CENTRAL_SEQ_OPTION); 170 } 171 172 cpu_suspend(0, exynos_aftr_finisher); 173 174 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 175 scu_enable(S5P_VA_SCU); 176 if (call_firmware_op(resume) == -ENOSYS) 177 exynos_cpu_restore_register(); 178 } 179 180 exynos_pm_central_resume(); 181 182 if (soc_is_exynos3250()) 183 exynos_clear_boot_flag(cpuid, C2_STATE); 184 185 cpu_pm_exit(); 186 } 187 188 #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE) 189 static atomic_t cpu1_wakeup = ATOMIC_INIT(0); 190 191 static int exynos_cpu0_enter_aftr(void) 192 { 193 int ret = -1; 194 195 /* 196 * If the other cpu is powered on, we have to power it off, because 197 * the AFTR state won't work otherwise 198 */ 199 if (cpu_online(1)) { 200 /* 201 * We reach a sync point with the coupled idle state, we know 202 * the other cpu will power down itself or will abort the 203 * sequence, let's wait for one of these to happen 204 */ 205 while (exynos_cpu_power_state(1)) { 206 unsigned long boot_addr; 207 208 /* 209 * The other cpu may skip idle and boot back 210 * up again 211 */ 212 if (atomic_read(&cpu1_wakeup)) 213 goto abort; 214 215 /* 216 * The other cpu may bounce through idle and 217 * boot back up again, getting stuck in the 218 * boot rom code 219 */ 220 ret = exynos_get_boot_addr(1, &boot_addr); 221 if (ret) 222 goto fail; 223 ret = -1; 224 if (boot_addr == 0) 225 goto abort; 226 227 cpu_relax(); 228 } 229 } 230 231 exynos_enter_aftr(); 232 ret = 0; 233 234 abort: 235 if (cpu_online(1)) { 236 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume); 237 238 /* 239 * Set the boot vector to something non-zero 240 */ 241 ret = exynos_set_boot_addr(1, boot_addr); 242 if (ret) 243 goto fail; 244 dsb(); 245 246 /* 247 * Turn on cpu1 and wait for it to be on 248 */ 249 exynos_cpu_power_up(1); 250 while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN) 251 cpu_relax(); 252 253 if (soc_is_exynos3250()) { 254 while (!pmu_raw_readl(S5P_PMU_SPARE2) && 255 !atomic_read(&cpu1_wakeup)) 256 cpu_relax(); 257 258 if (!atomic_read(&cpu1_wakeup)) 259 exynos_core_restart(1); 260 } 261 262 while (!atomic_read(&cpu1_wakeup)) { 263 smp_rmb(); 264 265 /* 266 * Poke cpu1 out of the boot rom 267 */ 268 269 ret = exynos_set_boot_addr(1, boot_addr); 270 if (ret) 271 goto fail; 272 273 call_firmware_op(cpu_boot, 1); 274 dsb_sev(); 275 } 276 } 277 fail: 278 return ret; 279 } 280 281 static int exynos_wfi_finisher(unsigned long flags) 282 { 283 if (soc_is_exynos3250()) 284 flush_cache_all(); 285 cpu_do_idle(); 286 287 return -1; 288 } 289 290 static int exynos_cpu1_powerdown(void) 291 { 292 int ret = -1; 293 294 /* 295 * Idle sequence for cpu1 296 */ 297 if (cpu_pm_enter()) 298 goto cpu1_aborted; 299 300 /* 301 * Turn off cpu 1 302 */ 303 exynos_cpu_power_down(1); 304 305 if (soc_is_exynos3250()) 306 pmu_raw_writel(0, S5P_PMU_SPARE2); 307 308 ret = cpu_suspend(0, exynos_wfi_finisher); 309 310 cpu_pm_exit(); 311 312 cpu1_aborted: 313 dsb(); 314 /* 315 * Notify cpu 0 that cpu 1 is awake 316 */ 317 atomic_set(&cpu1_wakeup, 1); 318 319 return ret; 320 } 321 322 static void exynos_pre_enter_aftr(void) 323 { 324 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume); 325 326 (void)exynos_set_boot_addr(1, boot_addr); 327 } 328 329 static void exynos_post_enter_aftr(void) 330 { 331 atomic_set(&cpu1_wakeup, 0); 332 } 333 334 struct cpuidle_exynos_data cpuidle_coupled_exynos_data = { 335 .cpu0_enter_aftr = exynos_cpu0_enter_aftr, 336 .cpu1_powerdown = exynos_cpu1_powerdown, 337 .pre_enter_aftr = exynos_pre_enter_aftr, 338 .post_enter_aftr = exynos_post_enter_aftr, 339 }; 340 #endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */ 341