1c9347101SJongpill Lee /* 2c9347101SJongpill Lee * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 383014579SKukjin Kim * http://www.samsung.com 483014579SKukjin Kim * 5c9347101SJongpill Lee * EXYNOS - Power Management support 683014579SKukjin Kim * 783014579SKukjin Kim * Based on arch/arm/mach-s3c2410/pm.c 883014579SKukjin Kim * Copyright (c) 2006 Simtec Electronics 983014579SKukjin Kim * Ben Dooks <ben@simtec.co.uk> 1083014579SKukjin Kim * 1183014579SKukjin Kim * This program is free software; you can redistribute it and/or modify 1283014579SKukjin Kim * it under the terms of the GNU General Public License version 2 as 1383014579SKukjin Kim * published by the Free Software Foundation. 1483014579SKukjin Kim */ 1583014579SKukjin Kim 1683014579SKukjin Kim #include <linux/init.h> 1783014579SKukjin Kim #include <linux/suspend.h> 1883014579SKukjin Kim #include <linux/syscore_ops.h> 1983014579SKukjin Kim #include <linux/io.h> 2083014579SKukjin Kim #include <linux/err.h> 2183014579SKukjin Kim #include <linux/clk.h> 2283014579SKukjin Kim 2383014579SKukjin Kim #include <asm/cacheflush.h> 2483014579SKukjin Kim #include <asm/hardware/cache-l2x0.h> 2563b870f1SShawn Guo #include <asm/smp_scu.h> 2683014579SKukjin Kim 2783014579SKukjin Kim #include <plat/cpu.h> 2883014579SKukjin Kim #include <plat/pm.h> 2983014579SKukjin Kim #include <plat/pll.h> 3083014579SKukjin Kim #include <plat/regs-srom.h> 3183014579SKukjin Kim 3283014579SKukjin Kim #include <mach/regs-irq.h> 3383014579SKukjin Kim #include <mach/regs-gpio.h> 3483014579SKukjin Kim #include <mach/regs-clock.h> 3583014579SKukjin Kim #include <mach/regs-pmu.h> 3683014579SKukjin Kim #include <mach/pm-core.h> 3783014579SKukjin Kim #include <mach/pmu.h> 3883014579SKukjin Kim 3983014579SKukjin Kim static struct sleep_save exynos4_set_clksrc[] = { 40a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, 41a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, 42a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, 43a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 44a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 45a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 46a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 47a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, 48a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, 4983014579SKukjin Kim }; 5083014579SKukjin Kim 5183014579SKukjin Kim static struct sleep_save exynos4210_set_clksrc[] = { 52a855039eSKukjin Kim { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, 5383014579SKukjin Kim }; 5483014579SKukjin Kim 5583014579SKukjin Kim static struct sleep_save exynos4_epll_save[] = { 56a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_EPLL_CON0), 57a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_EPLL_CON1), 5883014579SKukjin Kim }; 5983014579SKukjin Kim 6083014579SKukjin Kim static struct sleep_save exynos4_vpll_save[] = { 61a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_VPLL_CON0), 62a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_VPLL_CON1), 6383014579SKukjin Kim }; 6483014579SKukjin Kim 6586ffb0e8SAbhilash Kesavan static struct sleep_save exynos5_sys_save[] = { 6686ffb0e8SAbhilash Kesavan SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 6786ffb0e8SAbhilash Kesavan }; 6886ffb0e8SAbhilash Kesavan 69c9347101SJongpill Lee static struct sleep_save exynos_core_save[] = { 7083014579SKukjin Kim /* SROM side */ 7183014579SKukjin Kim SAVE_ITEM(S5P_SROM_BW), 7283014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC0), 7383014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC1), 7483014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC2), 7583014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC3), 7683014579SKukjin Kim }; 7783014579SKukjin Kim 7883014579SKukjin Kim 7983014579SKukjin Kim /* For Cortex-A9 Diagnostic and Power control register */ 8083014579SKukjin Kim static unsigned int save_arm_register[2]; 8183014579SKukjin Kim 82c9347101SJongpill Lee static int exynos_cpu_suspend(unsigned long arg) 8383014579SKukjin Kim { 8460e49ca6SJongpill Lee #ifdef CONFIG_CACHE_L2X0 8583014579SKukjin Kim outer_flush_all(); 8660e49ca6SJongpill Lee #endif 8783014579SKukjin Kim 88573e5bbeSAbhilash Kesavan if (soc_is_exynos5250()) 89573e5bbeSAbhilash Kesavan flush_cache_all(); 90573e5bbeSAbhilash Kesavan 9183014579SKukjin Kim /* issue the standby signal into the pm unit. */ 9283014579SKukjin Kim cpu_do_idle(); 9383014579SKukjin Kim 94d3fcacf5SAbhilash Kesavan pr_info("Failed to suspend the system\n"); 95d3fcacf5SAbhilash Kesavan return 1; /* Aborting suspend */ 9683014579SKukjin Kim } 9783014579SKukjin Kim 98c9347101SJongpill Lee static void exynos_pm_prepare(void) 9983014579SKukjin Kim { 10060e49ca6SJongpill Lee unsigned int tmp; 10183014579SKukjin Kim 102c9347101SJongpill Lee s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 10360e49ca6SJongpill Lee 10460e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 10583014579SKukjin Kim s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); 10683014579SKukjin Kim s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); 10760e49ca6SJongpill Lee } else { 10886ffb0e8SAbhilash Kesavan s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 10960e49ca6SJongpill Lee /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 11060e49ca6SJongpill Lee tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 11160e49ca6SJongpill Lee tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 11260e49ca6SJongpill Lee __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 11360e49ca6SJongpill Lee } 11483014579SKukjin Kim 11583014579SKukjin Kim /* Set value of power down register for sleep mode */ 11683014579SKukjin Kim 1177d44d2baSJongpill Lee exynos_sys_powerdown_conf(SYS_SLEEP); 11883014579SKukjin Kim __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 11983014579SKukjin Kim 12083014579SKukjin Kim /* ensure at least INFORM0 has the resume address */ 12183014579SKukjin Kim 12283014579SKukjin Kim __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); 12383014579SKukjin Kim 12483014579SKukjin Kim /* Before enter central sequence mode, clock src register have to set */ 12583014579SKukjin Kim 12660e49ca6SJongpill Lee if (!soc_is_exynos5250()) 12783014579SKukjin Kim s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); 12883014579SKukjin Kim 12983014579SKukjin Kim if (soc_is_exynos4210()) 13083014579SKukjin Kim s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); 13183014579SKukjin Kim 13283014579SKukjin Kim } 13383014579SKukjin Kim 134c9347101SJongpill Lee static int exynos_pm_add(struct device *dev, struct subsys_interface *sif) 13583014579SKukjin Kim { 136c9347101SJongpill Lee pm_cpu_prep = exynos_pm_prepare; 137c9347101SJongpill Lee pm_cpu_sleep = exynos_cpu_suspend; 13883014579SKukjin Kim 13983014579SKukjin Kim return 0; 14083014579SKukjin Kim } 14183014579SKukjin Kim 14283014579SKukjin Kim static unsigned long pll_base_rate; 14383014579SKukjin Kim 14483014579SKukjin Kim static void exynos4_restore_pll(void) 14583014579SKukjin Kim { 14683014579SKukjin Kim unsigned long pll_con, locktime, lockcnt; 14783014579SKukjin Kim unsigned long pll_in_rate; 14883014579SKukjin Kim unsigned int p_div, epll_wait = 0, vpll_wait = 0; 14983014579SKukjin Kim 15083014579SKukjin Kim if (pll_base_rate == 0) 15183014579SKukjin Kim return; 15283014579SKukjin Kim 15383014579SKukjin Kim pll_in_rate = pll_base_rate; 15483014579SKukjin Kim 15583014579SKukjin Kim /* EPLL */ 15683014579SKukjin Kim pll_con = exynos4_epll_save[0].val; 15783014579SKukjin Kim 15883014579SKukjin Kim if (pll_con & (1 << 31)) { 15983014579SKukjin Kim pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); 16083014579SKukjin Kim p_div = (pll_con >> PLL46XX_PDIV_SHIFT); 16183014579SKukjin Kim 16283014579SKukjin Kim pll_in_rate /= 1000000; 16383014579SKukjin Kim 16483014579SKukjin Kim locktime = (3000 / pll_in_rate) * p_div; 16583014579SKukjin Kim lockcnt = locktime * 10000 / (10000 / pll_in_rate); 16683014579SKukjin Kim 167a855039eSKukjin Kim __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); 16883014579SKukjin Kim 16983014579SKukjin Kim s3c_pm_do_restore_core(exynos4_epll_save, 17083014579SKukjin Kim ARRAY_SIZE(exynos4_epll_save)); 17183014579SKukjin Kim epll_wait = 1; 17283014579SKukjin Kim } 17383014579SKukjin Kim 17483014579SKukjin Kim pll_in_rate = pll_base_rate; 17583014579SKukjin Kim 17683014579SKukjin Kim /* VPLL */ 17783014579SKukjin Kim pll_con = exynos4_vpll_save[0].val; 17883014579SKukjin Kim 17983014579SKukjin Kim if (pll_con & (1 << 31)) { 18083014579SKukjin Kim pll_in_rate /= 1000000; 18183014579SKukjin Kim /* 750us */ 18283014579SKukjin Kim locktime = 750; 18383014579SKukjin Kim lockcnt = locktime * 10000 / (10000 / pll_in_rate); 18483014579SKukjin Kim 185a855039eSKukjin Kim __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); 18683014579SKukjin Kim 18783014579SKukjin Kim s3c_pm_do_restore_core(exynos4_vpll_save, 18883014579SKukjin Kim ARRAY_SIZE(exynos4_vpll_save)); 18983014579SKukjin Kim vpll_wait = 1; 19083014579SKukjin Kim } 19183014579SKukjin Kim 19283014579SKukjin Kim /* Wait PLL locking */ 19383014579SKukjin Kim 19483014579SKukjin Kim do { 19583014579SKukjin Kim if (epll_wait) { 196a855039eSKukjin Kim pll_con = __raw_readl(EXYNOS4_EPLL_CON0); 197a855039eSKukjin Kim if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) 19883014579SKukjin Kim epll_wait = 0; 19983014579SKukjin Kim } 20083014579SKukjin Kim 20183014579SKukjin Kim if (vpll_wait) { 202a855039eSKukjin Kim pll_con = __raw_readl(EXYNOS4_VPLL_CON0); 203a855039eSKukjin Kim if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) 20483014579SKukjin Kim vpll_wait = 0; 20583014579SKukjin Kim } 20683014579SKukjin Kim } while (epll_wait || vpll_wait); 20783014579SKukjin Kim } 20883014579SKukjin Kim 209c9347101SJongpill Lee static struct subsys_interface exynos_pm_interface = { 21060e49ca6SJongpill Lee .name = "exynos_pm", 2119ee6af9cSThomas Abraham .subsys = &exynos_subsys, 212c9347101SJongpill Lee .add_dev = exynos_pm_add, 21383014579SKukjin Kim }; 21483014579SKukjin Kim 215c9347101SJongpill Lee static __init int exynos_pm_drvinit(void) 21683014579SKukjin Kim { 21783014579SKukjin Kim struct clk *pll_base; 21883014579SKukjin Kim unsigned int tmp; 21983014579SKukjin Kim 22083014579SKukjin Kim s3c_pm_init(); 22183014579SKukjin Kim 22283014579SKukjin Kim /* All wakeup disable */ 22383014579SKukjin Kim 22483014579SKukjin Kim tmp = __raw_readl(S5P_WAKEUP_MASK); 22583014579SKukjin Kim tmp |= ((0xFF << 8) | (0x1F << 1)); 22683014579SKukjin Kim __raw_writel(tmp, S5P_WAKEUP_MASK); 22783014579SKukjin Kim 228c9347101SJongpill Lee if (!soc_is_exynos5250()) { 22983014579SKukjin Kim pll_base = clk_get(NULL, "xtal"); 23083014579SKukjin Kim 23183014579SKukjin Kim if (!IS_ERR(pll_base)) { 23283014579SKukjin Kim pll_base_rate = clk_get_rate(pll_base); 23383014579SKukjin Kim clk_put(pll_base); 23483014579SKukjin Kim } 23583014579SKukjin Kim } 23683014579SKukjin Kim 237c9347101SJongpill Lee return subsys_interface_register(&exynos_pm_interface); 238c9347101SJongpill Lee } 239c9347101SJongpill Lee arch_initcall(exynos_pm_drvinit); 240c9347101SJongpill Lee 241c9347101SJongpill Lee static int exynos_pm_suspend(void) 24283014579SKukjin Kim { 24383014579SKukjin Kim unsigned long tmp; 24483014579SKukjin Kim 24583014579SKukjin Kim /* Setting Central Sequence Register for power down mode */ 24683014579SKukjin Kim 24783014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 24883014579SKukjin Kim tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 24983014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 25083014579SKukjin Kim 25160e49ca6SJongpill Lee /* Setting SEQ_OPTION register */ 25283014579SKukjin Kim 25360e49ca6SJongpill Lee tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 25460e49ca6SJongpill Lee __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 25560e49ca6SJongpill Lee 25660e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 25783014579SKukjin Kim /* Save Power control register */ 25883014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 0" 25983014579SKukjin Kim : "=r" (tmp) : : "cc"); 26083014579SKukjin Kim save_arm_register[0] = tmp; 26183014579SKukjin Kim 26283014579SKukjin Kim /* Save Diagnostic register */ 26383014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 1" 26483014579SKukjin Kim : "=r" (tmp) : : "cc"); 26583014579SKukjin Kim save_arm_register[1] = tmp; 26660e49ca6SJongpill Lee } 26783014579SKukjin Kim 26883014579SKukjin Kim return 0; 26983014579SKukjin Kim } 27083014579SKukjin Kim 271c9347101SJongpill Lee static void exynos_pm_resume(void) 27283014579SKukjin Kim { 27383014579SKukjin Kim unsigned long tmp; 27483014579SKukjin Kim 27583014579SKukjin Kim /* 27683014579SKukjin Kim * If PMU failed while entering sleep mode, WFI will be 27783014579SKukjin Kim * ignored by PMU and then exiting cpu_do_idle(). 27883014579SKukjin Kim * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 27983014579SKukjin Kim * in this situation. 28083014579SKukjin Kim */ 28183014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 28283014579SKukjin Kim if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 28383014579SKukjin Kim tmp |= S5P_CENTRAL_LOWPWR_CFG; 28483014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 285d3fcacf5SAbhilash Kesavan /* clear the wakeup state register */ 286d3fcacf5SAbhilash Kesavan __raw_writel(0x0, S5P_WAKEUP_STAT); 28783014579SKukjin Kim /* No need to perform below restore code */ 28883014579SKukjin Kim goto early_wakeup; 28983014579SKukjin Kim } 29060e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 29183014579SKukjin Kim /* Restore Power control register */ 29283014579SKukjin Kim tmp = save_arm_register[0]; 29383014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 0" 29483014579SKukjin Kim : : "r" (tmp) 29583014579SKukjin Kim : "cc"); 29683014579SKukjin Kim 29783014579SKukjin Kim /* Restore Diagnostic register */ 29883014579SKukjin Kim tmp = save_arm_register[1]; 29983014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 1" 30083014579SKukjin Kim : : "r" (tmp) 30183014579SKukjin Kim : "cc"); 30260e49ca6SJongpill Lee } 30383014579SKukjin Kim 30483014579SKukjin Kim /* For release retention */ 30583014579SKukjin Kim 30683014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 30783014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 30883014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 30983014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 31083014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 31183014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 31283014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 31383014579SKukjin Kim 31486ffb0e8SAbhilash Kesavan if (soc_is_exynos5250()) 31586ffb0e8SAbhilash Kesavan s3c_pm_do_restore(exynos5_sys_save, 31686ffb0e8SAbhilash Kesavan ARRAY_SIZE(exynos5_sys_save)); 31786ffb0e8SAbhilash Kesavan 318c9347101SJongpill Lee s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 31983014579SKukjin Kim 32060e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 32183014579SKukjin Kim exynos4_restore_pll(); 32283014579SKukjin Kim 323556ef3e4SMarek Szyprowski #ifdef CONFIG_SMP 32463b870f1SShawn Guo scu_enable(S5P_VA_SCU); 325556ef3e4SMarek Szyprowski #endif 32660e49ca6SJongpill Lee } 32783014579SKukjin Kim 32883014579SKukjin Kim early_wakeup: 329ebee8541SInderpal Singh 330ebee8541SInderpal Singh /* Clear SLEEP mode set in INFORM1 */ 331ebee8541SInderpal Singh __raw_writel(0x0, S5P_INFORM1); 332ebee8541SInderpal Singh 33383014579SKukjin Kim return; 33483014579SKukjin Kim } 33583014579SKukjin Kim 336c9347101SJongpill Lee static struct syscore_ops exynos_pm_syscore_ops = { 337c9347101SJongpill Lee .suspend = exynos_pm_suspend, 338c9347101SJongpill Lee .resume = exynos_pm_resume, 33983014579SKukjin Kim }; 34083014579SKukjin Kim 34160e49ca6SJongpill Lee static __init int exynos_pm_syscore_init(void) 34283014579SKukjin Kim { 343c9347101SJongpill Lee register_syscore_ops(&exynos_pm_syscore_ops); 34483014579SKukjin Kim return 0; 34583014579SKukjin Kim } 34660e49ca6SJongpill Lee arch_initcall(exynos_pm_syscore_init); 347