1c9347101SJongpill Lee /* 2c9347101SJongpill Lee * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 383014579SKukjin Kim * http://www.samsung.com 483014579SKukjin Kim * 5c9347101SJongpill Lee * EXYNOS - Power Management support 683014579SKukjin Kim * 783014579SKukjin Kim * Based on arch/arm/mach-s3c2410/pm.c 883014579SKukjin Kim * Copyright (c) 2006 Simtec Electronics 983014579SKukjin Kim * Ben Dooks <ben@simtec.co.uk> 1083014579SKukjin Kim * 1183014579SKukjin Kim * This program is free software; you can redistribute it and/or modify 1283014579SKukjin Kim * it under the terms of the GNU General Public License version 2 as 1383014579SKukjin Kim * published by the Free Software Foundation. 1483014579SKukjin Kim */ 1583014579SKukjin Kim 1683014579SKukjin Kim #include <linux/init.h> 1783014579SKukjin Kim #include <linux/suspend.h> 1883014579SKukjin Kim #include <linux/syscore_ops.h> 1983014579SKukjin Kim #include <linux/io.h> 2083014579SKukjin Kim #include <linux/err.h> 2183014579SKukjin Kim #include <linux/clk.h> 2283014579SKukjin Kim 2383014579SKukjin Kim #include <asm/cacheflush.h> 2483014579SKukjin Kim #include <asm/hardware/cache-l2x0.h> 2563b870f1SShawn Guo #include <asm/smp_scu.h> 2683014579SKukjin Kim 2783014579SKukjin Kim #include <plat/cpu.h> 2883014579SKukjin Kim #include <plat/pm.h> 2983014579SKukjin Kim #include <plat/pll.h> 3083014579SKukjin Kim #include <plat/regs-srom.h> 3183014579SKukjin Kim 329c9239afSKukjin Kim #include <mach/map.h> 3383014579SKukjin Kim #include <mach/pm-core.h> 34ccd458c1SKukjin Kim 35ccd458c1SKukjin Kim #include "common.h" 3665c9a853SKukjin Kim #include "regs-pmu.h" 3783014579SKukjin Kim 389c9239afSKukjin Kim #define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) 399c9239afSKukjin Kim #define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) 409c9239afSKukjin Kim 419c9239afSKukjin Kim #define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) 429c9239afSKukjin Kim #define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) 439c9239afSKukjin Kim #define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) 449c9239afSKukjin Kim #define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) 459c9239afSKukjin Kim 469c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) 479c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) 489c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) 499c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) 509c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) 519c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) 529c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) 539c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) 549c9239afSKukjin Kim 559c9239afSKukjin Kim #define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) 569c9239afSKukjin Kim 579c9239afSKukjin Kim #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) 589c9239afSKukjin Kim #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) 599c9239afSKukjin Kim 609c9239afSKukjin Kim #define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) 619c9239afSKukjin Kim 627c394e7bSDaniel Kurtz static const struct sleep_save exynos4_set_clksrc[] = { 63a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, 64a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, 65a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, 66a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 67a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 68a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 69a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 70a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, 71a855039eSKukjin Kim { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, 7283014579SKukjin Kim }; 7383014579SKukjin Kim 747c394e7bSDaniel Kurtz static const struct sleep_save exynos4210_set_clksrc[] = { 75a855039eSKukjin Kim { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, 7683014579SKukjin Kim }; 7783014579SKukjin Kim 7883014579SKukjin Kim static struct sleep_save exynos4_epll_save[] = { 79a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_EPLL_CON0), 80a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_EPLL_CON1), 8183014579SKukjin Kim }; 8283014579SKukjin Kim 8383014579SKukjin Kim static struct sleep_save exynos4_vpll_save[] = { 84a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_VPLL_CON0), 85a855039eSKukjin Kim SAVE_ITEM(EXYNOS4_VPLL_CON1), 8683014579SKukjin Kim }; 8783014579SKukjin Kim 8886ffb0e8SAbhilash Kesavan static struct sleep_save exynos5_sys_save[] = { 8986ffb0e8SAbhilash Kesavan SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 9086ffb0e8SAbhilash Kesavan }; 9186ffb0e8SAbhilash Kesavan 92c9347101SJongpill Lee static struct sleep_save exynos_core_save[] = { 9383014579SKukjin Kim /* SROM side */ 9483014579SKukjin Kim SAVE_ITEM(S5P_SROM_BW), 9583014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC0), 9683014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC1), 9783014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC2), 9883014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC3), 9983014579SKukjin Kim }; 10083014579SKukjin Kim 10183014579SKukjin Kim 10283014579SKukjin Kim /* For Cortex-A9 Diagnostic and Power control register */ 10383014579SKukjin Kim static unsigned int save_arm_register[2]; 10483014579SKukjin Kim 105c9347101SJongpill Lee static int exynos_cpu_suspend(unsigned long arg) 10683014579SKukjin Kim { 10760e49ca6SJongpill Lee #ifdef CONFIG_CACHE_L2X0 10883014579SKukjin Kim outer_flush_all(); 10960e49ca6SJongpill Lee #endif 11083014579SKukjin Kim 111573e5bbeSAbhilash Kesavan if (soc_is_exynos5250()) 112573e5bbeSAbhilash Kesavan flush_cache_all(); 113573e5bbeSAbhilash Kesavan 11483014579SKukjin Kim /* issue the standby signal into the pm unit. */ 11583014579SKukjin Kim cpu_do_idle(); 11683014579SKukjin Kim 117d3fcacf5SAbhilash Kesavan pr_info("Failed to suspend the system\n"); 118d3fcacf5SAbhilash Kesavan return 1; /* Aborting suspend */ 11983014579SKukjin Kim } 12083014579SKukjin Kim 121c9347101SJongpill Lee static void exynos_pm_prepare(void) 12283014579SKukjin Kim { 12360e49ca6SJongpill Lee unsigned int tmp; 12483014579SKukjin Kim 125c9347101SJongpill Lee s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 12660e49ca6SJongpill Lee 12760e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 12883014579SKukjin Kim s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); 12983014579SKukjin Kim s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); 13060e49ca6SJongpill Lee } else { 13186ffb0e8SAbhilash Kesavan s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 13260e49ca6SJongpill Lee /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 13360e49ca6SJongpill Lee tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 13460e49ca6SJongpill Lee tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 13560e49ca6SJongpill Lee __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 13660e49ca6SJongpill Lee } 13783014579SKukjin Kim 13883014579SKukjin Kim /* Set value of power down register for sleep mode */ 13983014579SKukjin Kim 1407d44d2baSJongpill Lee exynos_sys_powerdown_conf(SYS_SLEEP); 14183014579SKukjin Kim __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 14283014579SKukjin Kim 14383014579SKukjin Kim /* ensure at least INFORM0 has the resume address */ 14483014579SKukjin Kim 14583014579SKukjin Kim __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); 14683014579SKukjin Kim 14783014579SKukjin Kim /* Before enter central sequence mode, clock src register have to set */ 14883014579SKukjin Kim 14960e49ca6SJongpill Lee if (!soc_is_exynos5250()) 15083014579SKukjin Kim s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); 15183014579SKukjin Kim 15283014579SKukjin Kim if (soc_is_exynos4210()) 15383014579SKukjin Kim s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); 15483014579SKukjin Kim 15583014579SKukjin Kim } 15683014579SKukjin Kim 157c9347101SJongpill Lee static int exynos_pm_add(struct device *dev, struct subsys_interface *sif) 15883014579SKukjin Kim { 159c9347101SJongpill Lee pm_cpu_prep = exynos_pm_prepare; 160c9347101SJongpill Lee pm_cpu_sleep = exynos_cpu_suspend; 16183014579SKukjin Kim 16283014579SKukjin Kim return 0; 16383014579SKukjin Kim } 16483014579SKukjin Kim 16583014579SKukjin Kim static unsigned long pll_base_rate; 16683014579SKukjin Kim 16783014579SKukjin Kim static void exynos4_restore_pll(void) 16883014579SKukjin Kim { 16983014579SKukjin Kim unsigned long pll_con, locktime, lockcnt; 17083014579SKukjin Kim unsigned long pll_in_rate; 17183014579SKukjin Kim unsigned int p_div, epll_wait = 0, vpll_wait = 0; 17283014579SKukjin Kim 17383014579SKukjin Kim if (pll_base_rate == 0) 17483014579SKukjin Kim return; 17583014579SKukjin Kim 17683014579SKukjin Kim pll_in_rate = pll_base_rate; 17783014579SKukjin Kim 17883014579SKukjin Kim /* EPLL */ 17983014579SKukjin Kim pll_con = exynos4_epll_save[0].val; 18083014579SKukjin Kim 18183014579SKukjin Kim if (pll_con & (1 << 31)) { 18283014579SKukjin Kim pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); 18383014579SKukjin Kim p_div = (pll_con >> PLL46XX_PDIV_SHIFT); 18483014579SKukjin Kim 18583014579SKukjin Kim pll_in_rate /= 1000000; 18683014579SKukjin Kim 18783014579SKukjin Kim locktime = (3000 / pll_in_rate) * p_div; 18883014579SKukjin Kim lockcnt = locktime * 10000 / (10000 / pll_in_rate); 18983014579SKukjin Kim 190a855039eSKukjin Kim __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); 19183014579SKukjin Kim 19283014579SKukjin Kim s3c_pm_do_restore_core(exynos4_epll_save, 19383014579SKukjin Kim ARRAY_SIZE(exynos4_epll_save)); 19483014579SKukjin Kim epll_wait = 1; 19583014579SKukjin Kim } 19683014579SKukjin Kim 19783014579SKukjin Kim pll_in_rate = pll_base_rate; 19883014579SKukjin Kim 19983014579SKukjin Kim /* VPLL */ 20083014579SKukjin Kim pll_con = exynos4_vpll_save[0].val; 20183014579SKukjin Kim 20283014579SKukjin Kim if (pll_con & (1 << 31)) { 20383014579SKukjin Kim pll_in_rate /= 1000000; 20483014579SKukjin Kim /* 750us */ 20583014579SKukjin Kim locktime = 750; 20683014579SKukjin Kim lockcnt = locktime * 10000 / (10000 / pll_in_rate); 20783014579SKukjin Kim 208a855039eSKukjin Kim __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); 20983014579SKukjin Kim 21083014579SKukjin Kim s3c_pm_do_restore_core(exynos4_vpll_save, 21183014579SKukjin Kim ARRAY_SIZE(exynos4_vpll_save)); 21283014579SKukjin Kim vpll_wait = 1; 21383014579SKukjin Kim } 21483014579SKukjin Kim 21583014579SKukjin Kim /* Wait PLL locking */ 21683014579SKukjin Kim 21783014579SKukjin Kim do { 21883014579SKukjin Kim if (epll_wait) { 219a855039eSKukjin Kim pll_con = __raw_readl(EXYNOS4_EPLL_CON0); 220a855039eSKukjin Kim if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) 22183014579SKukjin Kim epll_wait = 0; 22283014579SKukjin Kim } 22383014579SKukjin Kim 22483014579SKukjin Kim if (vpll_wait) { 225a855039eSKukjin Kim pll_con = __raw_readl(EXYNOS4_VPLL_CON0); 226a855039eSKukjin Kim if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) 22783014579SKukjin Kim vpll_wait = 0; 22883014579SKukjin Kim } 22983014579SKukjin Kim } while (epll_wait || vpll_wait); 23083014579SKukjin Kim } 23183014579SKukjin Kim 232c9347101SJongpill Lee static struct subsys_interface exynos_pm_interface = { 23360e49ca6SJongpill Lee .name = "exynos_pm", 2349ee6af9cSThomas Abraham .subsys = &exynos_subsys, 235c9347101SJongpill Lee .add_dev = exynos_pm_add, 23683014579SKukjin Kim }; 23783014579SKukjin Kim 238c9347101SJongpill Lee static __init int exynos_pm_drvinit(void) 23983014579SKukjin Kim { 24083014579SKukjin Kim struct clk *pll_base; 24183014579SKukjin Kim unsigned int tmp; 24283014579SKukjin Kim 243e085cad6SKukjin Kim if (soc_is_exynos5440()) 244e085cad6SKukjin Kim return 0; 245e085cad6SKukjin Kim 24683014579SKukjin Kim s3c_pm_init(); 24783014579SKukjin Kim 24883014579SKukjin Kim /* All wakeup disable */ 24983014579SKukjin Kim 25083014579SKukjin Kim tmp = __raw_readl(S5P_WAKEUP_MASK); 25183014579SKukjin Kim tmp |= ((0xFF << 8) | (0x1F << 1)); 25283014579SKukjin Kim __raw_writel(tmp, S5P_WAKEUP_MASK); 25383014579SKukjin Kim 254c9347101SJongpill Lee if (!soc_is_exynos5250()) { 25583014579SKukjin Kim pll_base = clk_get(NULL, "xtal"); 25683014579SKukjin Kim 25783014579SKukjin Kim if (!IS_ERR(pll_base)) { 25883014579SKukjin Kim pll_base_rate = clk_get_rate(pll_base); 25983014579SKukjin Kim clk_put(pll_base); 26083014579SKukjin Kim } 26183014579SKukjin Kim } 26283014579SKukjin Kim 263c9347101SJongpill Lee return subsys_interface_register(&exynos_pm_interface); 264c9347101SJongpill Lee } 265c9347101SJongpill Lee arch_initcall(exynos_pm_drvinit); 266c9347101SJongpill Lee 267c9347101SJongpill Lee static int exynos_pm_suspend(void) 26883014579SKukjin Kim { 26983014579SKukjin Kim unsigned long tmp; 27083014579SKukjin Kim 27183014579SKukjin Kim /* Setting Central Sequence Register for power down mode */ 27283014579SKukjin Kim 27383014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 27483014579SKukjin Kim tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 27583014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 27683014579SKukjin Kim 27760e49ca6SJongpill Lee /* Setting SEQ_OPTION register */ 27883014579SKukjin Kim 27960e49ca6SJongpill Lee tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 28060e49ca6SJongpill Lee __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 28160e49ca6SJongpill Lee 28260e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 28383014579SKukjin Kim /* Save Power control register */ 28483014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 0" 28583014579SKukjin Kim : "=r" (tmp) : : "cc"); 28683014579SKukjin Kim save_arm_register[0] = tmp; 28783014579SKukjin Kim 28883014579SKukjin Kim /* Save Diagnostic register */ 28983014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 1" 29083014579SKukjin Kim : "=r" (tmp) : : "cc"); 29183014579SKukjin Kim save_arm_register[1] = tmp; 29260e49ca6SJongpill Lee } 29383014579SKukjin Kim 29483014579SKukjin Kim return 0; 29583014579SKukjin Kim } 29683014579SKukjin Kim 297c9347101SJongpill Lee static void exynos_pm_resume(void) 29883014579SKukjin Kim { 29983014579SKukjin Kim unsigned long tmp; 30083014579SKukjin Kim 30183014579SKukjin Kim /* 30283014579SKukjin Kim * If PMU failed while entering sleep mode, WFI will be 30383014579SKukjin Kim * ignored by PMU and then exiting cpu_do_idle(). 30483014579SKukjin Kim * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 30583014579SKukjin Kim * in this situation. 30683014579SKukjin Kim */ 30783014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 30883014579SKukjin Kim if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 30983014579SKukjin Kim tmp |= S5P_CENTRAL_LOWPWR_CFG; 31083014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 311d3fcacf5SAbhilash Kesavan /* clear the wakeup state register */ 312d3fcacf5SAbhilash Kesavan __raw_writel(0x0, S5P_WAKEUP_STAT); 31383014579SKukjin Kim /* No need to perform below restore code */ 31483014579SKukjin Kim goto early_wakeup; 31583014579SKukjin Kim } 31660e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 31783014579SKukjin Kim /* Restore Power control register */ 31883014579SKukjin Kim tmp = save_arm_register[0]; 31983014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 0" 32083014579SKukjin Kim : : "r" (tmp) 32183014579SKukjin Kim : "cc"); 32283014579SKukjin Kim 32383014579SKukjin Kim /* Restore Diagnostic register */ 32483014579SKukjin Kim tmp = save_arm_register[1]; 32583014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 1" 32683014579SKukjin Kim : : "r" (tmp) 32783014579SKukjin Kim : "cc"); 32860e49ca6SJongpill Lee } 32983014579SKukjin Kim 33083014579SKukjin Kim /* For release retention */ 33183014579SKukjin Kim 33283014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 33383014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 33483014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 33583014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 33683014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 33783014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 33883014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 33983014579SKukjin Kim 34086ffb0e8SAbhilash Kesavan if (soc_is_exynos5250()) 34186ffb0e8SAbhilash Kesavan s3c_pm_do_restore(exynos5_sys_save, 34286ffb0e8SAbhilash Kesavan ARRAY_SIZE(exynos5_sys_save)); 34386ffb0e8SAbhilash Kesavan 344c9347101SJongpill Lee s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 34583014579SKukjin Kim 34660e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 34783014579SKukjin Kim exynos4_restore_pll(); 34883014579SKukjin Kim 349556ef3e4SMarek Szyprowski #ifdef CONFIG_SMP 35063b870f1SShawn Guo scu_enable(S5P_VA_SCU); 351556ef3e4SMarek Szyprowski #endif 35260e49ca6SJongpill Lee } 35383014579SKukjin Kim 35483014579SKukjin Kim early_wakeup: 355ebee8541SInderpal Singh 356ebee8541SInderpal Singh /* Clear SLEEP mode set in INFORM1 */ 357ebee8541SInderpal Singh __raw_writel(0x0, S5P_INFORM1); 358ebee8541SInderpal Singh 35983014579SKukjin Kim return; 36083014579SKukjin Kim } 36183014579SKukjin Kim 362c9347101SJongpill Lee static struct syscore_ops exynos_pm_syscore_ops = { 363c9347101SJongpill Lee .suspend = exynos_pm_suspend, 364c9347101SJongpill Lee .resume = exynos_pm_resume, 36583014579SKukjin Kim }; 36683014579SKukjin Kim 36760e49ca6SJongpill Lee static __init int exynos_pm_syscore_init(void) 36883014579SKukjin Kim { 369e085cad6SKukjin Kim if (soc_is_exynos5440()) 370e085cad6SKukjin Kim return 0; 371e085cad6SKukjin Kim 372c9347101SJongpill Lee register_syscore_ops(&exynos_pm_syscore_ops); 37383014579SKukjin Kim return 0; 37483014579SKukjin Kim } 37560e49ca6SJongpill Lee arch_initcall(exynos_pm_syscore_init); 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