1c9347101SJongpill Lee /* 2c9347101SJongpill Lee * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 383014579SKukjin Kim * http://www.samsung.com 483014579SKukjin Kim * 5c9347101SJongpill Lee * EXYNOS - Power Management support 683014579SKukjin Kim * 783014579SKukjin Kim * Based on arch/arm/mach-s3c2410/pm.c 883014579SKukjin Kim * Copyright (c) 2006 Simtec Electronics 983014579SKukjin Kim * Ben Dooks <ben@simtec.co.uk> 1083014579SKukjin Kim * 1183014579SKukjin Kim * This program is free software; you can redistribute it and/or modify 1283014579SKukjin Kim * it under the terms of the GNU General Public License version 2 as 1383014579SKukjin Kim * published by the Free Software Foundation. 1483014579SKukjin Kim */ 1583014579SKukjin Kim 1683014579SKukjin Kim #include <linux/init.h> 1783014579SKukjin Kim #include <linux/suspend.h> 1883014579SKukjin Kim #include <linux/syscore_ops.h> 1983014579SKukjin Kim #include <linux/io.h> 20dd8ac696STomasz Figa #include <linux/irqchip/arm-gic.h> 2183014579SKukjin Kim #include <linux/err.h> 2283014579SKukjin Kim #include <linux/clk.h> 2383014579SKukjin Kim 2483014579SKukjin Kim #include <asm/cacheflush.h> 2583014579SKukjin Kim #include <asm/hardware/cache-l2x0.h> 2663b870f1SShawn Guo #include <asm/smp_scu.h> 27d710aa31STomasz Figa #include <asm/suspend.h> 2883014579SKukjin Kim 2983014579SKukjin Kim #include <plat/cpu.h> 30d710aa31STomasz Figa #include <plat/pm-common.h> 3183014579SKukjin Kim #include <plat/pll.h> 3283014579SKukjin Kim #include <plat/regs-srom.h> 3383014579SKukjin Kim 349c9239afSKukjin Kim #include <mach/map.h> 35ccd458c1SKukjin Kim 36ccd458c1SKukjin Kim #include "common.h" 3765c9a853SKukjin Kim #include "regs-pmu.h" 3883014579SKukjin Kim 39dd8ac696STomasz Figa /** 40dd8ac696STomasz Figa * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping 41dd8ac696STomasz Figa * @hwirq: Hardware IRQ signal of the GIC 42dd8ac696STomasz Figa * @mask: Mask in PMU wake-up mask register 43dd8ac696STomasz Figa */ 44dd8ac696STomasz Figa struct exynos_wkup_irq { 45dd8ac696STomasz Figa unsigned int hwirq; 46dd8ac696STomasz Figa u32 mask; 47dd8ac696STomasz Figa }; 48dd8ac696STomasz Figa 4986ffb0e8SAbhilash Kesavan static struct sleep_save exynos5_sys_save[] = { 5086ffb0e8SAbhilash Kesavan SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 5186ffb0e8SAbhilash Kesavan }; 5286ffb0e8SAbhilash Kesavan 53c9347101SJongpill Lee static struct sleep_save exynos_core_save[] = { 5483014579SKukjin Kim /* SROM side */ 5583014579SKukjin Kim SAVE_ITEM(S5P_SROM_BW), 5683014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC0), 5783014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC1), 5883014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC2), 5983014579SKukjin Kim SAVE_ITEM(S5P_SROM_BC3), 6083014579SKukjin Kim }; 6183014579SKukjin Kim 62dd8ac696STomasz Figa /* 63dd8ac696STomasz Figa * GIC wake-up support 64dd8ac696STomasz Figa */ 65dd8ac696STomasz Figa 66d710aa31STomasz Figa static u32 exynos_irqwake_intmask = 0xffffffff; 6783014579SKukjin Kim 68dd8ac696STomasz Figa static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 69dd8ac696STomasz Figa { 76, BIT(1) }, /* RTC alarm */ 70dd8ac696STomasz Figa { 77, BIT(2) }, /* RTC tick */ 71dd8ac696STomasz Figa { /* sentinel */ }, 72dd8ac696STomasz Figa }; 73dd8ac696STomasz Figa 74dd8ac696STomasz Figa static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 75dd8ac696STomasz Figa { 75, BIT(1) }, /* RTC alarm */ 76dd8ac696STomasz Figa { 76, BIT(2) }, /* RTC tick */ 77dd8ac696STomasz Figa { /* sentinel */ }, 78dd8ac696STomasz Figa }; 79dd8ac696STomasz Figa 80dd8ac696STomasz Figa static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 81dd8ac696STomasz Figa { 82dd8ac696STomasz Figa const struct exynos_wkup_irq *wkup_irq; 83dd8ac696STomasz Figa 84dd8ac696STomasz Figa if (soc_is_exynos5250()) 85dd8ac696STomasz Figa wkup_irq = exynos5250_wkup_irq; 86dd8ac696STomasz Figa else 87dd8ac696STomasz Figa wkup_irq = exynos4_wkup_irq; 88dd8ac696STomasz Figa 89dd8ac696STomasz Figa while (wkup_irq->mask) { 90dd8ac696STomasz Figa if (wkup_irq->hwirq == data->hwirq) { 91dd8ac696STomasz Figa if (!state) 92dd8ac696STomasz Figa exynos_irqwake_intmask |= wkup_irq->mask; 93dd8ac696STomasz Figa else 94dd8ac696STomasz Figa exynos_irqwake_intmask &= ~wkup_irq->mask; 95dd8ac696STomasz Figa return 0; 96dd8ac696STomasz Figa } 97dd8ac696STomasz Figa ++wkup_irq; 98dd8ac696STomasz Figa } 99dd8ac696STomasz Figa 100dd8ac696STomasz Figa return -ENOENT; 101dd8ac696STomasz Figa } 102dd8ac696STomasz Figa 103d3af6976SLeela Krishna Amudala /** 104d3af6976SLeela Krishna Amudala * exynos_core_power_down : power down the specified cpu 105d3af6976SLeela Krishna Amudala * @cpu : the cpu to power down 106d3af6976SLeela Krishna Amudala * 107d3af6976SLeela Krishna Amudala * Power down the specified cpu. The sequence must be finished by a 108d3af6976SLeela Krishna Amudala * call to cpu_do_idle() 109d3af6976SLeela Krishna Amudala * 110d3af6976SLeela Krishna Amudala */ 111d3af6976SLeela Krishna Amudala void exynos_cpu_power_down(int cpu) 112d3af6976SLeela Krishna Amudala { 113d3af6976SLeela Krishna Amudala __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 114d3af6976SLeela Krishna Amudala } 115d3af6976SLeela Krishna Amudala 116d3af6976SLeela Krishna Amudala /** 117d3af6976SLeela Krishna Amudala * exynos_cpu_power_up : power up the specified cpu 118d3af6976SLeela Krishna Amudala * @cpu : the cpu to power up 119d3af6976SLeela Krishna Amudala * 120d3af6976SLeela Krishna Amudala * Power up the specified cpu 121d3af6976SLeela Krishna Amudala */ 122d3af6976SLeela Krishna Amudala void exynos_cpu_power_up(int cpu) 123d3af6976SLeela Krishna Amudala { 124d3af6976SLeela Krishna Amudala __raw_writel(S5P_CORE_LOCAL_PWR_EN, 125d3af6976SLeela Krishna Amudala EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 126d3af6976SLeela Krishna Amudala } 127d3af6976SLeela Krishna Amudala 128d3af6976SLeela Krishna Amudala /** 129d3af6976SLeela Krishna Amudala * exynos_cpu_power_state : returns the power state of the cpu 130d3af6976SLeela Krishna Amudala * @cpu : the cpu to retrieve the power state from 131d3af6976SLeela Krishna Amudala * 132d3af6976SLeela Krishna Amudala */ 133d3af6976SLeela Krishna Amudala int exynos_cpu_power_state(int cpu) 134d3af6976SLeela Krishna Amudala { 135d3af6976SLeela Krishna Amudala return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 136d3af6976SLeela Krishna Amudala S5P_CORE_LOCAL_PWR_EN); 137d3af6976SLeela Krishna Amudala } 138d3af6976SLeela Krishna Amudala 139096d21c6SAbhilash Kesavan /** 140096d21c6SAbhilash Kesavan * exynos_cluster_power_down : power down the specified cluster 141096d21c6SAbhilash Kesavan * @cluster : the cluster to power down 142096d21c6SAbhilash Kesavan */ 143096d21c6SAbhilash Kesavan void exynos_cluster_power_down(int cluster) 144096d21c6SAbhilash Kesavan { 145096d21c6SAbhilash Kesavan __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 146096d21c6SAbhilash Kesavan } 147096d21c6SAbhilash Kesavan 148096d21c6SAbhilash Kesavan /** 149096d21c6SAbhilash Kesavan * exynos_cluster_power_up : power up the specified cluster 150096d21c6SAbhilash Kesavan * @cluster : the cluster to power up 151096d21c6SAbhilash Kesavan */ 152096d21c6SAbhilash Kesavan void exynos_cluster_power_up(int cluster) 153096d21c6SAbhilash Kesavan { 154096d21c6SAbhilash Kesavan __raw_writel(S5P_CORE_LOCAL_PWR_EN, 155096d21c6SAbhilash Kesavan EXYNOS_COMMON_CONFIGURATION(cluster)); 156096d21c6SAbhilash Kesavan } 157096d21c6SAbhilash Kesavan 158096d21c6SAbhilash Kesavan /** 159096d21c6SAbhilash Kesavan * exynos_cluster_power_state : returns the power state of the cluster 160096d21c6SAbhilash Kesavan * @cluster : the cluster to retrieve the power state from 161096d21c6SAbhilash Kesavan * 162096d21c6SAbhilash Kesavan */ 163096d21c6SAbhilash Kesavan int exynos_cluster_power_state(int cluster) 164096d21c6SAbhilash Kesavan { 165096d21c6SAbhilash Kesavan return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 166096d21c6SAbhilash Kesavan S5P_CORE_LOCAL_PWR_EN); 167096d21c6SAbhilash Kesavan } 168096d21c6SAbhilash Kesavan 16983014579SKukjin Kim /* For Cortex-A9 Diagnostic and Power control register */ 17083014579SKukjin Kim static unsigned int save_arm_register[2]; 17183014579SKukjin Kim 172c9347101SJongpill Lee static int exynos_cpu_suspend(unsigned long arg) 17383014579SKukjin Kim { 17460e49ca6SJongpill Lee #ifdef CONFIG_CACHE_L2X0 17583014579SKukjin Kim outer_flush_all(); 17660e49ca6SJongpill Lee #endif 17783014579SKukjin Kim 178573e5bbeSAbhilash Kesavan if (soc_is_exynos5250()) 179573e5bbeSAbhilash Kesavan flush_cache_all(); 180573e5bbeSAbhilash Kesavan 18183014579SKukjin Kim /* issue the standby signal into the pm unit. */ 18283014579SKukjin Kim cpu_do_idle(); 18383014579SKukjin Kim 184d3fcacf5SAbhilash Kesavan pr_info("Failed to suspend the system\n"); 185d3fcacf5SAbhilash Kesavan return 1; /* Aborting suspend */ 18683014579SKukjin Kim } 18783014579SKukjin Kim 188c9347101SJongpill Lee static void exynos_pm_prepare(void) 18983014579SKukjin Kim { 19060e49ca6SJongpill Lee unsigned int tmp; 19183014579SKukjin Kim 192d710aa31STomasz Figa /* Set wake-up mask registers */ 193d710aa31STomasz Figa __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 194d710aa31STomasz Figa __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 195d710aa31STomasz Figa 196c9347101SJongpill Lee s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 19760e49ca6SJongpill Lee 198e11d919eSTomasz Figa if (soc_is_exynos5250()) { 19986ffb0e8SAbhilash Kesavan s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 20060e49ca6SJongpill Lee /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 20160e49ca6SJongpill Lee tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 20260e49ca6SJongpill Lee tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 20360e49ca6SJongpill Lee __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 20460e49ca6SJongpill Lee } 20583014579SKukjin Kim 20683014579SKukjin Kim /* Set value of power down register for sleep mode */ 20783014579SKukjin Kim 2087d44d2baSJongpill Lee exynos_sys_powerdown_conf(SYS_SLEEP); 20983014579SKukjin Kim __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 21083014579SKukjin Kim 21183014579SKukjin Kim /* ensure at least INFORM0 has the resume address */ 21283014579SKukjin Kim 213d710aa31STomasz Figa __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 21483014579SKukjin Kim } 21583014579SKukjin Kim 216c9347101SJongpill Lee static int exynos_pm_suspend(void) 21783014579SKukjin Kim { 21883014579SKukjin Kim unsigned long tmp; 21983014579SKukjin Kim 22083014579SKukjin Kim /* Setting Central Sequence Register for power down mode */ 22183014579SKukjin Kim 22283014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 22383014579SKukjin Kim tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 22483014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 22583014579SKukjin Kim 22660e49ca6SJongpill Lee /* Setting SEQ_OPTION register */ 22783014579SKukjin Kim 22860e49ca6SJongpill Lee tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 22960e49ca6SJongpill Lee __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 23060e49ca6SJongpill Lee 23160e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 23283014579SKukjin Kim /* Save Power control register */ 23383014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 0" 23483014579SKukjin Kim : "=r" (tmp) : : "cc"); 23583014579SKukjin Kim save_arm_register[0] = tmp; 23683014579SKukjin Kim 23783014579SKukjin Kim /* Save Diagnostic register */ 23883014579SKukjin Kim asm ("mrc p15, 0, %0, c15, c0, 1" 23983014579SKukjin Kim : "=r" (tmp) : : "cc"); 24083014579SKukjin Kim save_arm_register[1] = tmp; 24160e49ca6SJongpill Lee } 24283014579SKukjin Kim 24383014579SKukjin Kim return 0; 24483014579SKukjin Kim } 24583014579SKukjin Kim 246c9347101SJongpill Lee static void exynos_pm_resume(void) 24783014579SKukjin Kim { 24883014579SKukjin Kim unsigned long tmp; 24983014579SKukjin Kim 25083014579SKukjin Kim /* 25183014579SKukjin Kim * If PMU failed while entering sleep mode, WFI will be 25283014579SKukjin Kim * ignored by PMU and then exiting cpu_do_idle(). 25383014579SKukjin Kim * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 25483014579SKukjin Kim * in this situation. 25583014579SKukjin Kim */ 25683014579SKukjin Kim tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 25783014579SKukjin Kim if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 25883014579SKukjin Kim tmp |= S5P_CENTRAL_LOWPWR_CFG; 25983014579SKukjin Kim __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 260d3fcacf5SAbhilash Kesavan /* clear the wakeup state register */ 261d3fcacf5SAbhilash Kesavan __raw_writel(0x0, S5P_WAKEUP_STAT); 26283014579SKukjin Kim /* No need to perform below restore code */ 26383014579SKukjin Kim goto early_wakeup; 26483014579SKukjin Kim } 26560e49ca6SJongpill Lee if (!soc_is_exynos5250()) { 26683014579SKukjin Kim /* Restore Power control register */ 26783014579SKukjin Kim tmp = save_arm_register[0]; 26883014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 0" 26983014579SKukjin Kim : : "r" (tmp) 27083014579SKukjin Kim : "cc"); 27183014579SKukjin Kim 27283014579SKukjin Kim /* Restore Diagnostic register */ 27383014579SKukjin Kim tmp = save_arm_register[1]; 27483014579SKukjin Kim asm volatile ("mcr p15, 0, %0, c15, c0, 1" 27583014579SKukjin Kim : : "r" (tmp) 27683014579SKukjin Kim : "cc"); 27760e49ca6SJongpill Lee } 27883014579SKukjin Kim 27983014579SKukjin Kim /* For release retention */ 28083014579SKukjin Kim 28183014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 28283014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 28383014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 28483014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 28583014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 28683014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 28783014579SKukjin Kim __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 28883014579SKukjin Kim 28986ffb0e8SAbhilash Kesavan if (soc_is_exynos5250()) 29086ffb0e8SAbhilash Kesavan s3c_pm_do_restore(exynos5_sys_save, 29186ffb0e8SAbhilash Kesavan ARRAY_SIZE(exynos5_sys_save)); 29286ffb0e8SAbhilash Kesavan 293c9347101SJongpill Lee s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 29483014579SKukjin Kim 295e11d919eSTomasz Figa if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250()) 29663b870f1SShawn Guo scu_enable(S5P_VA_SCU); 29783014579SKukjin Kim 29883014579SKukjin Kim early_wakeup: 299ebee8541SInderpal Singh 300ebee8541SInderpal Singh /* Clear SLEEP mode set in INFORM1 */ 301ebee8541SInderpal Singh __raw_writel(0x0, S5P_INFORM1); 302ebee8541SInderpal Singh 30383014579SKukjin Kim return; 30483014579SKukjin Kim } 30583014579SKukjin Kim 306c9347101SJongpill Lee static struct syscore_ops exynos_pm_syscore_ops = { 307c9347101SJongpill Lee .suspend = exynos_pm_suspend, 308c9347101SJongpill Lee .resume = exynos_pm_resume, 30983014579SKukjin Kim }; 31083014579SKukjin Kim 311d710aa31STomasz Figa /* 312d710aa31STomasz Figa * Suspend Ops 313d710aa31STomasz Figa */ 314d710aa31STomasz Figa 315d710aa31STomasz Figa static int exynos_suspend_enter(suspend_state_t state) 316d710aa31STomasz Figa { 317d710aa31STomasz Figa int ret; 318d710aa31STomasz Figa 319d710aa31STomasz Figa s3c_pm_debug_init(); 320d710aa31STomasz Figa 321d710aa31STomasz Figa S3C_PMDBG("%s: suspending the system...\n", __func__); 322d710aa31STomasz Figa 323d710aa31STomasz Figa S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 324d710aa31STomasz Figa exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 325d710aa31STomasz Figa 326d710aa31STomasz Figa if (exynos_irqwake_intmask == -1U 327d710aa31STomasz Figa && exynos_get_eint_wake_mask() == -1U) { 328d710aa31STomasz Figa pr_err("%s: No wake-up sources!\n", __func__); 329d710aa31STomasz Figa pr_err("%s: Aborting sleep\n", __func__); 330d710aa31STomasz Figa return -EINVAL; 331d710aa31STomasz Figa } 332d710aa31STomasz Figa 333d710aa31STomasz Figa s3c_pm_save_uarts(); 334d710aa31STomasz Figa exynos_pm_prepare(); 335d710aa31STomasz Figa flush_cache_all(); 336d710aa31STomasz Figa s3c_pm_check_store(); 337d710aa31STomasz Figa 338d710aa31STomasz Figa ret = cpu_suspend(0, exynos_cpu_suspend); 339d710aa31STomasz Figa if (ret) 340d710aa31STomasz Figa return ret; 341d710aa31STomasz Figa 342d710aa31STomasz Figa s3c_pm_restore_uarts(); 343d710aa31STomasz Figa 344d710aa31STomasz Figa S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 345d710aa31STomasz Figa __raw_readl(S5P_WAKEUP_STAT)); 346d710aa31STomasz Figa 347d710aa31STomasz Figa s3c_pm_check_restore(); 348d710aa31STomasz Figa 349d710aa31STomasz Figa S3C_PMDBG("%s: resuming the system...\n", __func__); 350d710aa31STomasz Figa 351d710aa31STomasz Figa return 0; 352d710aa31STomasz Figa } 353d710aa31STomasz Figa 354d710aa31STomasz Figa static int exynos_suspend_prepare(void) 355d710aa31STomasz Figa { 356d710aa31STomasz Figa s3c_pm_check_prepare(); 357d710aa31STomasz Figa 358d710aa31STomasz Figa return 0; 359d710aa31STomasz Figa } 360d710aa31STomasz Figa 361d710aa31STomasz Figa static void exynos_suspend_finish(void) 362d710aa31STomasz Figa { 363d710aa31STomasz Figa s3c_pm_check_cleanup(); 364d710aa31STomasz Figa } 365d710aa31STomasz Figa 366d710aa31STomasz Figa static const struct platform_suspend_ops exynos_suspend_ops = { 367d710aa31STomasz Figa .enter = exynos_suspend_enter, 368d710aa31STomasz Figa .prepare = exynos_suspend_prepare, 369d710aa31STomasz Figa .finish = exynos_suspend_finish, 370d710aa31STomasz Figa .valid = suspend_valid_only_mem, 371d710aa31STomasz Figa }; 372d710aa31STomasz Figa 373559ba237STomasz Figa void __init exynos_pm_init(void) 37483014579SKukjin Kim { 375559ba237STomasz Figa u32 tmp; 376559ba237STomasz Figa 377dd8ac696STomasz Figa /* Platform-specific GIC callback */ 378dd8ac696STomasz Figa gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 379dd8ac696STomasz Figa 380559ba237STomasz Figa /* All wakeup disable */ 381559ba237STomasz Figa tmp = __raw_readl(S5P_WAKEUP_MASK); 382559ba237STomasz Figa tmp |= ((0xFF << 8) | (0x1F << 1)); 383559ba237STomasz Figa __raw_writel(tmp, S5P_WAKEUP_MASK); 384e085cad6SKukjin Kim 385c9347101SJongpill Lee register_syscore_ops(&exynos_pm_syscore_ops); 386d710aa31STomasz Figa suspend_set_ops(&exynos_suspend_ops); 38783014579SKukjin Kim } 388