1 /* linux/arch/arm/mach-exynos4/platsmp.c 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 7 * 8 * Copyright (C) 2002 ARM Ltd. 9 * All Rights Reserved 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/smp_plat.h> 26 #include <asm/smp_scu.h> 27 #include <asm/firmware.h> 28 29 #include <mach/hardware.h> 30 #include <mach/regs-clock.h> 31 #include <mach/regs-pmu.h> 32 33 #include <plat/cpu.h> 34 35 #include "common.h" 36 37 extern void exynos4_secondary_startup(void); 38 39 static inline void __iomem *cpu_boot_reg_base(void) 40 { 41 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 42 return S5P_INFORM5; 43 return S5P_VA_SYSRAM; 44 } 45 46 static inline void __iomem *cpu_boot_reg(int cpu) 47 { 48 void __iomem *boot_reg; 49 50 boot_reg = cpu_boot_reg_base(); 51 if (soc_is_exynos4412()) 52 boot_reg += 4*cpu; 53 return boot_reg; 54 } 55 56 /* 57 * Write pen_release in a way that is guaranteed to be visible to all 58 * observers, irrespective of whether they're taking part in coherency 59 * or not. This is necessary for the hotplug code to work reliably. 60 */ 61 static void write_pen_release(int val) 62 { 63 pen_release = val; 64 smp_wmb(); 65 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 66 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); 67 } 68 69 static void __iomem *scu_base_addr(void) 70 { 71 return (void __iomem *)(S5P_VA_SCU); 72 } 73 74 static DEFINE_SPINLOCK(boot_lock); 75 76 static void __cpuinit exynos_secondary_init(unsigned int cpu) 77 { 78 /* 79 * let the primary processor know we're out of the 80 * pen, then head off into the C entry point 81 */ 82 write_pen_release(-1); 83 84 /* 85 * Synchronise with the boot thread. 86 */ 87 spin_lock(&boot_lock); 88 spin_unlock(&boot_lock); 89 } 90 91 static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 92 { 93 unsigned long timeout; 94 unsigned long phys_cpu = cpu_logical_map(cpu); 95 96 /* 97 * Set synchronisation state between this boot processor 98 * and the secondary one 99 */ 100 spin_lock(&boot_lock); 101 102 /* 103 * The secondary processor is waiting to be released from 104 * the holding pen - release it, then wait for it to flag 105 * that it has been released by resetting pen_release. 106 * 107 * Note that "pen_release" is the hardware CPU ID, whereas 108 * "cpu" is Linux's internal ID. 109 */ 110 write_pen_release(phys_cpu); 111 112 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { 113 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 114 S5P_ARM_CORE1_CONFIGURATION); 115 116 timeout = 10; 117 118 /* wait max 10 ms until cpu1 is on */ 119 while ((__raw_readl(S5P_ARM_CORE1_STATUS) 120 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { 121 if (timeout-- == 0) 122 break; 123 124 mdelay(1); 125 } 126 127 if (timeout == 0) { 128 printk(KERN_ERR "cpu1 power enable failed"); 129 spin_unlock(&boot_lock); 130 return -ETIMEDOUT; 131 } 132 } 133 /* 134 * Send the secondary CPU a soft interrupt, thereby causing 135 * the boot monitor to read the system wide flags register, 136 * and branch to the address found there. 137 */ 138 139 timeout = jiffies + (1 * HZ); 140 while (time_before(jiffies, timeout)) { 141 unsigned long boot_addr; 142 143 smp_rmb(); 144 145 boot_addr = virt_to_phys(exynos4_secondary_startup); 146 147 /* 148 * Try to set boot address using firmware first 149 * and fall back to boot register if it fails. 150 */ 151 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr)) 152 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 153 154 call_firmware_op(cpu_boot, phys_cpu); 155 156 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 157 158 if (pen_release == -1) 159 break; 160 161 udelay(10); 162 } 163 164 /* 165 * now the secondary core is starting up let it run its 166 * calibrations, then wait for it to finish 167 */ 168 spin_unlock(&boot_lock); 169 170 return pen_release != -1 ? -ENOSYS : 0; 171 } 172 173 /* 174 * Initialise the CPU possible map early - this describes the CPUs 175 * which may be present or become present in the system. 176 */ 177 178 static void __init exynos_smp_init_cpus(void) 179 { 180 void __iomem *scu_base = scu_base_addr(); 181 unsigned int i, ncores; 182 183 if (soc_is_exynos5250()) 184 ncores = 2; 185 else 186 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 187 188 /* sanity check */ 189 if (ncores > nr_cpu_ids) { 190 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 191 ncores, nr_cpu_ids); 192 ncores = nr_cpu_ids; 193 } 194 195 for (i = 0; i < ncores; i++) 196 set_cpu_possible(i, true); 197 } 198 199 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 200 { 201 int i; 202 203 if (!(soc_is_exynos5250() || soc_is_exynos5440())) 204 scu_enable(scu_base_addr()); 205 206 /* 207 * Write the address of secondary startup into the 208 * system-wide flags register. The boot monitor waits 209 * until it receives a soft interrupt, and then the 210 * secondary CPU branches to this address. 211 * 212 * Try using firmware operation first and fall back to 213 * boot register if it fails. 214 */ 215 for (i = 1; i < max_cpus; ++i) { 216 unsigned long phys_cpu; 217 unsigned long boot_addr; 218 219 phys_cpu = cpu_logical_map(i); 220 boot_addr = virt_to_phys(exynos4_secondary_startup); 221 222 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr)) 223 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 224 } 225 } 226 227 struct smp_operations exynos_smp_ops __initdata = { 228 .smp_init_cpus = exynos_smp_init_cpus, 229 .smp_prepare_cpus = exynos_smp_prepare_cpus, 230 .smp_secondary_init = exynos_secondary_init, 231 .smp_boot_secondary = exynos_boot_secondary, 232 #ifdef CONFIG_HOTPLUG_CPU 233 .cpu_die = exynos_cpu_die, 234 #endif 235 }; 236