xref: /openbmc/linux/arch/arm/mach-exynos/platsmp.c (revision d2999e1b)
1 /* linux/arch/arm/mach-exynos4/platsmp.c
2  *
3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4  *		http://www.samsung.com
5  *
6  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7  *
8  *  Copyright (C) 2002 ARM Ltd.
9  *  All Rights Reserved
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14 */
15 
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
22 #include <linux/io.h>
23 #include <linux/of_address.h>
24 
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
29 
30 #include "common.h"
31 #include "regs-pmu.h"
32 
33 extern void exynos4_secondary_startup(void);
34 
35 static inline void __iomem *cpu_boot_reg_base(void)
36 {
37 	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
38 		return S5P_INFORM5;
39 	return sysram_base_addr;
40 }
41 
42 static inline void __iomem *cpu_boot_reg(int cpu)
43 {
44 	void __iomem *boot_reg;
45 
46 	boot_reg = cpu_boot_reg_base();
47 	if (!boot_reg)
48 		return ERR_PTR(-ENODEV);
49 	if (soc_is_exynos4412())
50 		boot_reg += 4*cpu;
51 	else if (soc_is_exynos5420() || soc_is_exynos5800())
52 		boot_reg += 4;
53 	return boot_reg;
54 }
55 
56 /*
57  * Write pen_release in a way that is guaranteed to be visible to all
58  * observers, irrespective of whether they're taking part in coherency
59  * or not.  This is necessary for the hotplug code to work reliably.
60  */
61 static void write_pen_release(int val)
62 {
63 	pen_release = val;
64 	smp_wmb();
65 	sync_cache_w(&pen_release);
66 }
67 
68 static void __iomem *scu_base_addr(void)
69 {
70 	return (void __iomem *)(S5P_VA_SCU);
71 }
72 
73 static DEFINE_SPINLOCK(boot_lock);
74 
75 static void exynos_secondary_init(unsigned int cpu)
76 {
77 	/*
78 	 * let the primary processor know we're out of the
79 	 * pen, then head off into the C entry point
80 	 */
81 	write_pen_release(-1);
82 
83 	/*
84 	 * Synchronise with the boot thread.
85 	 */
86 	spin_lock(&boot_lock);
87 	spin_unlock(&boot_lock);
88 }
89 
90 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
91 {
92 	unsigned long timeout;
93 	unsigned long phys_cpu = cpu_logical_map(cpu);
94 	int ret = -ENOSYS;
95 
96 	/*
97 	 * Set synchronisation state between this boot processor
98 	 * and the secondary one
99 	 */
100 	spin_lock(&boot_lock);
101 
102 	/*
103 	 * The secondary processor is waiting to be released from
104 	 * the holding pen - release it, then wait for it to flag
105 	 * that it has been released by resetting pen_release.
106 	 *
107 	 * Note that "pen_release" is the hardware CPU ID, whereas
108 	 * "cpu" is Linux's internal ID.
109 	 */
110 	write_pen_release(phys_cpu);
111 
112 	if (!exynos_cpu_power_state(cpu)) {
113 		exynos_cpu_power_up(cpu);
114 		timeout = 10;
115 
116 		/* wait max 10 ms until cpu1 is on */
117 		while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
118 			if (timeout-- == 0)
119 				break;
120 
121 			mdelay(1);
122 		}
123 
124 		if (timeout == 0) {
125 			printk(KERN_ERR "cpu1 power enable failed");
126 			spin_unlock(&boot_lock);
127 			return -ETIMEDOUT;
128 		}
129 	}
130 	/*
131 	 * Send the secondary CPU a soft interrupt, thereby causing
132 	 * the boot monitor to read the system wide flags register,
133 	 * and branch to the address found there.
134 	 */
135 
136 	timeout = jiffies + (1 * HZ);
137 	while (time_before(jiffies, timeout)) {
138 		unsigned long boot_addr;
139 
140 		smp_rmb();
141 
142 		boot_addr = virt_to_phys(exynos4_secondary_startup);
143 
144 		/*
145 		 * Try to set boot address using firmware first
146 		 * and fall back to boot register if it fails.
147 		 */
148 		ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
149 		if (ret && ret != -ENOSYS)
150 			goto fail;
151 		if (ret == -ENOSYS) {
152 			void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
153 
154 			if (IS_ERR(boot_reg)) {
155 				ret = PTR_ERR(boot_reg);
156 				goto fail;
157 			}
158 			__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
159 		}
160 
161 		call_firmware_op(cpu_boot, phys_cpu);
162 
163 		arch_send_wakeup_ipi_mask(cpumask_of(cpu));
164 
165 		if (pen_release == -1)
166 			break;
167 
168 		udelay(10);
169 	}
170 
171 	/*
172 	 * now the secondary core is starting up let it run its
173 	 * calibrations, then wait for it to finish
174 	 */
175 fail:
176 	spin_unlock(&boot_lock);
177 
178 	return pen_release != -1 ? ret : 0;
179 }
180 
181 /*
182  * Initialise the CPU possible map early - this describes the CPUs
183  * which may be present or become present in the system.
184  */
185 
186 static void __init exynos_smp_init_cpus(void)
187 {
188 	void __iomem *scu_base = scu_base_addr();
189 	unsigned int i, ncores;
190 
191 	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
192 		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
193 	else
194 		/*
195 		 * CPU Nodes are passed thru DT and set_cpu_possible
196 		 * is set by "arm_dt_init_cpu_maps".
197 		 */
198 		return;
199 
200 	/* sanity check */
201 	if (ncores > nr_cpu_ids) {
202 		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
203 			ncores, nr_cpu_ids);
204 		ncores = nr_cpu_ids;
205 	}
206 
207 	for (i = 0; i < ncores; i++)
208 		set_cpu_possible(i, true);
209 }
210 
211 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
212 {
213 	int i;
214 
215 	exynos_sysram_init();
216 
217 	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
218 		scu_enable(scu_base_addr());
219 
220 	/*
221 	 * Write the address of secondary startup into the
222 	 * system-wide flags register. The boot monitor waits
223 	 * until it receives a soft interrupt, and then the
224 	 * secondary CPU branches to this address.
225 	 *
226 	 * Try using firmware operation first and fall back to
227 	 * boot register if it fails.
228 	 */
229 	for (i = 1; i < max_cpus; ++i) {
230 		unsigned long phys_cpu;
231 		unsigned long boot_addr;
232 		int ret;
233 
234 		phys_cpu = cpu_logical_map(i);
235 		boot_addr = virt_to_phys(exynos4_secondary_startup);
236 
237 		ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
238 		if (ret && ret != -ENOSYS)
239 			break;
240 		if (ret == -ENOSYS) {
241 			void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
242 
243 			if (IS_ERR(boot_reg))
244 				break;
245 			__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
246 		}
247 	}
248 }
249 
250 struct smp_operations exynos_smp_ops __initdata = {
251 	.smp_init_cpus		= exynos_smp_init_cpus,
252 	.smp_prepare_cpus	= exynos_smp_prepare_cpus,
253 	.smp_secondary_init	= exynos_secondary_init,
254 	.smp_boot_secondary	= exynos_boot_secondary,
255 #ifdef CONFIG_HOTPLUG_CPU
256 	.cpu_die		= exynos_cpu_die,
257 #endif
258 };
259