1 /* linux/arch/arm/mach-exynos4/platsmp.c 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 7 * 8 * Copyright (C) 2002 ARM Ltd. 9 * All Rights Reserved 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/hardware/gic.h> 26 #include <asm/smp_plat.h> 27 #include <asm/smp_scu.h> 28 29 #include <mach/hardware.h> 30 #include <mach/regs-clock.h> 31 #include <mach/regs-pmu.h> 32 33 #include <plat/cpu.h> 34 35 extern void exynos4_secondary_startup(void); 36 37 #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 38 S5P_INFORM5 : S5P_VA_SYSRAM) 39 40 /* 41 * control for which core is the next to come out of the secondary 42 * boot "holding pen" 43 */ 44 45 volatile int __cpuinitdata pen_release = -1; 46 47 /* 48 * Write pen_release in a way that is guaranteed to be visible to all 49 * observers, irrespective of whether they're taking part in coherency 50 * or not. This is necessary for the hotplug code to work reliably. 51 */ 52 static void write_pen_release(int val) 53 { 54 pen_release = val; 55 smp_wmb(); 56 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 57 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); 58 } 59 60 static void __iomem *scu_base_addr(void) 61 { 62 return (void __iomem *)(S5P_VA_SCU); 63 } 64 65 static DEFINE_SPINLOCK(boot_lock); 66 67 void __cpuinit platform_secondary_init(unsigned int cpu) 68 { 69 /* 70 * if any interrupts are already enabled for the primary 71 * core (e.g. timer irq), then they will not have been enabled 72 * for us: do so 73 */ 74 gic_secondary_init(0); 75 76 /* 77 * let the primary processor know we're out of the 78 * pen, then head off into the C entry point 79 */ 80 write_pen_release(-1); 81 82 /* 83 * Synchronise with the boot thread. 84 */ 85 spin_lock(&boot_lock); 86 spin_unlock(&boot_lock); 87 } 88 89 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 90 { 91 unsigned long timeout; 92 93 /* 94 * Set synchronisation state between this boot processor 95 * and the secondary one 96 */ 97 spin_lock(&boot_lock); 98 99 /* 100 * The secondary processor is waiting to be released from 101 * the holding pen - release it, then wait for it to flag 102 * that it has been released by resetting pen_release. 103 * 104 * Note that "pen_release" is the hardware CPU ID, whereas 105 * "cpu" is Linux's internal ID. 106 */ 107 write_pen_release(cpu_logical_map(cpu)); 108 109 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { 110 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 111 S5P_ARM_CORE1_CONFIGURATION); 112 113 timeout = 10; 114 115 /* wait max 10 ms until cpu1 is on */ 116 while ((__raw_readl(S5P_ARM_CORE1_STATUS) 117 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { 118 if (timeout-- == 0) 119 break; 120 121 mdelay(1); 122 } 123 124 if (timeout == 0) { 125 printk(KERN_ERR "cpu1 power enable failed"); 126 spin_unlock(&boot_lock); 127 return -ETIMEDOUT; 128 } 129 } 130 /* 131 * Send the secondary CPU a soft interrupt, thereby causing 132 * the boot monitor to read the system wide flags register, 133 * and branch to the address found there. 134 */ 135 136 timeout = jiffies + (1 * HZ); 137 while (time_before(jiffies, timeout)) { 138 smp_rmb(); 139 140 __raw_writel(virt_to_phys(exynos4_secondary_startup), 141 CPU1_BOOT_REG); 142 gic_raise_softirq(cpumask_of(cpu), 1); 143 144 if (pen_release == -1) 145 break; 146 147 udelay(10); 148 } 149 150 /* 151 * now the secondary core is starting up let it run its 152 * calibrations, then wait for it to finish 153 */ 154 spin_unlock(&boot_lock); 155 156 return pen_release != -1 ? -ENOSYS : 0; 157 } 158 159 /* 160 * Initialise the CPU possible map early - this describes the CPUs 161 * which may be present or become present in the system. 162 */ 163 164 void __init smp_init_cpus(void) 165 { 166 void __iomem *scu_base = scu_base_addr(); 167 unsigned int i, ncores; 168 169 if (soc_is_exynos5250()) 170 ncores = 2; 171 else 172 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 173 174 /* sanity check */ 175 if (ncores > nr_cpu_ids) { 176 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 177 ncores, nr_cpu_ids); 178 ncores = nr_cpu_ids; 179 } 180 181 for (i = 0; i < ncores; i++) 182 set_cpu_possible(i, true); 183 184 set_smp_cross_call(gic_raise_softirq); 185 } 186 187 void __init platform_smp_prepare_cpus(unsigned int max_cpus) 188 { 189 if (!soc_is_exynos5250()) 190 scu_enable(scu_base_addr()); 191 192 /* 193 * Write the address of secondary startup into the 194 * system-wide flags register. The boot monitor waits 195 * until it receives a soft interrupt, and then the 196 * secondary CPU branches to this address. 197 */ 198 __raw_writel(virt_to_phys(exynos4_secondary_startup), 199 CPU1_BOOT_REG); 200 } 201