1 /* linux/arch/arm/mach-exynos4/platsmp.c 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 7 * 8 * Copyright (C) 2002 ARM Ltd. 9 * All Rights Reserved 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/of_address.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/smp_plat.h> 27 #include <asm/smp_scu.h> 28 #include <asm/firmware.h> 29 30 #include "common.h" 31 #include "regs-pmu.h" 32 33 extern void exynos4_secondary_startup(void); 34 35 void __iomem *sysram_base_addr; 36 void __iomem *sysram_ns_base_addr; 37 38 static void __init exynos_smp_prepare_sysram(void) 39 { 40 struct device_node *node; 41 42 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") { 43 if (!of_device_is_available(node)) 44 continue; 45 sysram_base_addr = of_iomap(node, 0); 46 break; 47 } 48 49 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") { 50 if (!of_device_is_available(node)) 51 continue; 52 sysram_ns_base_addr = of_iomap(node, 0); 53 break; 54 } 55 } 56 57 static inline void __iomem *cpu_boot_reg_base(void) 58 { 59 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 60 return S5P_INFORM5; 61 return sysram_base_addr; 62 } 63 64 static inline void __iomem *cpu_boot_reg(int cpu) 65 { 66 void __iomem *boot_reg; 67 68 boot_reg = cpu_boot_reg_base(); 69 if (!boot_reg) 70 return ERR_PTR(-ENODEV); 71 if (soc_is_exynos4412()) 72 boot_reg += 4*cpu; 73 else if (soc_is_exynos5420() || soc_is_exynos5800()) 74 boot_reg += 4; 75 return boot_reg; 76 } 77 78 /* 79 * Write pen_release in a way that is guaranteed to be visible to all 80 * observers, irrespective of whether they're taking part in coherency 81 * or not. This is necessary for the hotplug code to work reliably. 82 */ 83 static void write_pen_release(int val) 84 { 85 pen_release = val; 86 smp_wmb(); 87 sync_cache_w(&pen_release); 88 } 89 90 static void __iomem *scu_base_addr(void) 91 { 92 return (void __iomem *)(S5P_VA_SCU); 93 } 94 95 static DEFINE_SPINLOCK(boot_lock); 96 97 static void exynos_secondary_init(unsigned int cpu) 98 { 99 /* 100 * let the primary processor know we're out of the 101 * pen, then head off into the C entry point 102 */ 103 write_pen_release(-1); 104 105 /* 106 * Synchronise with the boot thread. 107 */ 108 spin_lock(&boot_lock); 109 spin_unlock(&boot_lock); 110 } 111 112 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 113 { 114 unsigned long timeout; 115 unsigned long phys_cpu = cpu_logical_map(cpu); 116 int ret = -ENOSYS; 117 118 /* 119 * Set synchronisation state between this boot processor 120 * and the secondary one 121 */ 122 spin_lock(&boot_lock); 123 124 /* 125 * The secondary processor is waiting to be released from 126 * the holding pen - release it, then wait for it to flag 127 * that it has been released by resetting pen_release. 128 * 129 * Note that "pen_release" is the hardware CPU ID, whereas 130 * "cpu" is Linux's internal ID. 131 */ 132 write_pen_release(phys_cpu); 133 134 if (!exynos_cpu_power_state(cpu)) { 135 exynos_cpu_power_up(cpu); 136 timeout = 10; 137 138 /* wait max 10 ms until cpu1 is on */ 139 while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) { 140 if (timeout-- == 0) 141 break; 142 143 mdelay(1); 144 } 145 146 if (timeout == 0) { 147 printk(KERN_ERR "cpu1 power enable failed"); 148 spin_unlock(&boot_lock); 149 return -ETIMEDOUT; 150 } 151 } 152 /* 153 * Send the secondary CPU a soft interrupt, thereby causing 154 * the boot monitor to read the system wide flags register, 155 * and branch to the address found there. 156 */ 157 158 timeout = jiffies + (1 * HZ); 159 while (time_before(jiffies, timeout)) { 160 unsigned long boot_addr; 161 162 smp_rmb(); 163 164 boot_addr = virt_to_phys(exynos4_secondary_startup); 165 166 /* 167 * Try to set boot address using firmware first 168 * and fall back to boot register if it fails. 169 */ 170 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr); 171 if (ret && ret != -ENOSYS) 172 goto fail; 173 if (ret == -ENOSYS) { 174 void __iomem *boot_reg = cpu_boot_reg(phys_cpu); 175 176 if (IS_ERR(boot_reg)) { 177 ret = PTR_ERR(boot_reg); 178 goto fail; 179 } 180 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 181 } 182 183 call_firmware_op(cpu_boot, phys_cpu); 184 185 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 186 187 if (pen_release == -1) 188 break; 189 190 udelay(10); 191 } 192 193 /* 194 * now the secondary core is starting up let it run its 195 * calibrations, then wait for it to finish 196 */ 197 fail: 198 spin_unlock(&boot_lock); 199 200 return pen_release != -1 ? ret : 0; 201 } 202 203 /* 204 * Initialise the CPU possible map early - this describes the CPUs 205 * which may be present or become present in the system. 206 */ 207 208 static void __init exynos_smp_init_cpus(void) 209 { 210 void __iomem *scu_base = scu_base_addr(); 211 unsigned int i, ncores; 212 213 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 214 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 215 else 216 /* 217 * CPU Nodes are passed thru DT and set_cpu_possible 218 * is set by "arm_dt_init_cpu_maps". 219 */ 220 return; 221 222 /* sanity check */ 223 if (ncores > nr_cpu_ids) { 224 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 225 ncores, nr_cpu_ids); 226 ncores = nr_cpu_ids; 227 } 228 229 for (i = 0; i < ncores; i++) 230 set_cpu_possible(i, true); 231 } 232 233 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 234 { 235 int i; 236 237 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 238 scu_enable(scu_base_addr()); 239 240 exynos_smp_prepare_sysram(); 241 242 /* 243 * Write the address of secondary startup into the 244 * system-wide flags register. The boot monitor waits 245 * until it receives a soft interrupt, and then the 246 * secondary CPU branches to this address. 247 * 248 * Try using firmware operation first and fall back to 249 * boot register if it fails. 250 */ 251 for (i = 1; i < max_cpus; ++i) { 252 unsigned long phys_cpu; 253 unsigned long boot_addr; 254 int ret; 255 256 phys_cpu = cpu_logical_map(i); 257 boot_addr = virt_to_phys(exynos4_secondary_startup); 258 259 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr); 260 if (ret && ret != -ENOSYS) 261 break; 262 if (ret == -ENOSYS) { 263 void __iomem *boot_reg = cpu_boot_reg(phys_cpu); 264 265 if (IS_ERR(boot_reg)) 266 break; 267 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 268 } 269 } 270 } 271 272 struct smp_operations exynos_smp_ops __initdata = { 273 .smp_init_cpus = exynos_smp_init_cpus, 274 .smp_prepare_cpus = exynos_smp_prepare_cpus, 275 .smp_secondary_init = exynos_secondary_init, 276 .smp_boot_secondary = exynos_boot_secondary, 277 #ifdef CONFIG_HOTPLUG_CPU 278 .cpu_die = exynos_cpu_die, 279 #endif 280 }; 281