1 /* linux/arch/arm/mach-exynos4/platsmp.c 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 7 * 8 * Copyright (C) 2002 ARM Ltd. 9 * All Rights Reserved 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/of_address.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/smp_plat.h> 27 #include <asm/smp_scu.h> 28 #include <asm/firmware.h> 29 30 #include "common.h" 31 #include "regs-pmu.h" 32 33 extern void exynos4_secondary_startup(void); 34 35 static inline void __iomem *cpu_boot_reg_base(void) 36 { 37 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 38 return S5P_INFORM5; 39 return sysram_base_addr; 40 } 41 42 static inline void __iomem *cpu_boot_reg(int cpu) 43 { 44 void __iomem *boot_reg; 45 46 boot_reg = cpu_boot_reg_base(); 47 if (!boot_reg) 48 return ERR_PTR(-ENODEV); 49 if (soc_is_exynos4412()) 50 boot_reg += 4*cpu; 51 else if (soc_is_exynos5420() || soc_is_exynos5800()) 52 boot_reg += 4; 53 return boot_reg; 54 } 55 56 /* 57 * Write pen_release in a way that is guaranteed to be visible to all 58 * observers, irrespective of whether they're taking part in coherency 59 * or not. This is necessary for the hotplug code to work reliably. 60 */ 61 static void write_pen_release(int val) 62 { 63 pen_release = val; 64 smp_wmb(); 65 sync_cache_w(&pen_release); 66 } 67 68 static void __iomem *scu_base_addr(void) 69 { 70 return (void __iomem *)(S5P_VA_SCU); 71 } 72 73 static DEFINE_SPINLOCK(boot_lock); 74 75 static void exynos_secondary_init(unsigned int cpu) 76 { 77 /* 78 * let the primary processor know we're out of the 79 * pen, then head off into the C entry point 80 */ 81 write_pen_release(-1); 82 83 /* 84 * Synchronise with the boot thread. 85 */ 86 spin_lock(&boot_lock); 87 spin_unlock(&boot_lock); 88 } 89 90 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 91 { 92 unsigned long timeout; 93 u32 mpidr = cpu_logical_map(cpu); 94 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 95 int ret = -ENOSYS; 96 97 /* 98 * Set synchronisation state between this boot processor 99 * and the secondary one 100 */ 101 spin_lock(&boot_lock); 102 103 /* 104 * The secondary processor is waiting to be released from 105 * the holding pen - release it, then wait for it to flag 106 * that it has been released by resetting pen_release. 107 * 108 * Note that "pen_release" is the hardware CPU core ID, whereas 109 * "cpu" is Linux's internal ID. 110 */ 111 write_pen_release(core_id); 112 113 if (!exynos_cpu_power_state(core_id)) { 114 exynos_cpu_power_up(core_id); 115 timeout = 10; 116 117 /* wait max 10 ms until cpu1 is on */ 118 while (exynos_cpu_power_state(core_id) 119 != S5P_CORE_LOCAL_PWR_EN) { 120 if (timeout-- == 0) 121 break; 122 123 mdelay(1); 124 } 125 126 if (timeout == 0) { 127 printk(KERN_ERR "cpu1 power enable failed"); 128 spin_unlock(&boot_lock); 129 return -ETIMEDOUT; 130 } 131 } 132 /* 133 * Send the secondary CPU a soft interrupt, thereby causing 134 * the boot monitor to read the system wide flags register, 135 * and branch to the address found there. 136 */ 137 138 timeout = jiffies + (1 * HZ); 139 while (time_before(jiffies, timeout)) { 140 unsigned long boot_addr; 141 142 smp_rmb(); 143 144 boot_addr = virt_to_phys(exynos4_secondary_startup); 145 146 /* 147 * Try to set boot address using firmware first 148 * and fall back to boot register if it fails. 149 */ 150 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); 151 if (ret && ret != -ENOSYS) 152 goto fail; 153 if (ret == -ENOSYS) { 154 void __iomem *boot_reg = cpu_boot_reg(core_id); 155 156 if (IS_ERR(boot_reg)) { 157 ret = PTR_ERR(boot_reg); 158 goto fail; 159 } 160 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 161 } 162 163 call_firmware_op(cpu_boot, core_id); 164 165 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 166 167 if (pen_release == -1) 168 break; 169 170 udelay(10); 171 } 172 173 /* 174 * now the secondary core is starting up let it run its 175 * calibrations, then wait for it to finish 176 */ 177 fail: 178 spin_unlock(&boot_lock); 179 180 return pen_release != -1 ? ret : 0; 181 } 182 183 /* 184 * Initialise the CPU possible map early - this describes the CPUs 185 * which may be present or become present in the system. 186 */ 187 188 static void __init exynos_smp_init_cpus(void) 189 { 190 void __iomem *scu_base = scu_base_addr(); 191 unsigned int i, ncores; 192 193 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 194 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 195 else 196 /* 197 * CPU Nodes are passed thru DT and set_cpu_possible 198 * is set by "arm_dt_init_cpu_maps". 199 */ 200 return; 201 202 /* sanity check */ 203 if (ncores > nr_cpu_ids) { 204 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 205 ncores, nr_cpu_ids); 206 ncores = nr_cpu_ids; 207 } 208 209 for (i = 0; i < ncores; i++) 210 set_cpu_possible(i, true); 211 } 212 213 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 214 { 215 int i; 216 217 exynos_sysram_init(); 218 219 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 220 scu_enable(scu_base_addr()); 221 222 /* 223 * Write the address of secondary startup into the 224 * system-wide flags register. The boot monitor waits 225 * until it receives a soft interrupt, and then the 226 * secondary CPU branches to this address. 227 * 228 * Try using firmware operation first and fall back to 229 * boot register if it fails. 230 */ 231 for (i = 1; i < max_cpus; ++i) { 232 unsigned long boot_addr; 233 u32 mpidr; 234 u32 core_id; 235 int ret; 236 237 mpidr = cpu_logical_map(i); 238 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 239 boot_addr = virt_to_phys(exynos4_secondary_startup); 240 241 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); 242 if (ret && ret != -ENOSYS) 243 break; 244 if (ret == -ENOSYS) { 245 void __iomem *boot_reg = cpu_boot_reg(core_id); 246 247 if (IS_ERR(boot_reg)) 248 break; 249 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 250 } 251 } 252 } 253 254 struct smp_operations exynos_smp_ops __initdata = { 255 .smp_init_cpus = exynos_smp_init_cpus, 256 .smp_prepare_cpus = exynos_smp_prepare_cpus, 257 .smp_secondary_init = exynos_secondary_init, 258 .smp_boot_secondary = exynos_boot_secondary, 259 #ifdef CONFIG_HOTPLUG_CPU 260 .cpu_die = exynos_cpu_die, 261 #endif 262 }; 263