1 /* linux/arch/arm/mach-exynos4/platsmp.c 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 7 * 8 * Copyright (C) 2002 ARM Ltd. 9 * All Rights Reserved 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/hardware/gic.h> 26 #include <asm/smp_plat.h> 27 #include <asm/smp_scu.h> 28 29 #include <mach/hardware.h> 30 #include <mach/regs-clock.h> 31 #include <mach/regs-pmu.h> 32 33 #include <plat/cpu.h> 34 35 #include "common.h" 36 37 extern void exynos4_secondary_startup(void); 38 39 #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 40 S5P_INFORM5 : S5P_VA_SYSRAM) 41 42 /* 43 * Write pen_release in a way that is guaranteed to be visible to all 44 * observers, irrespective of whether they're taking part in coherency 45 * or not. This is necessary for the hotplug code to work reliably. 46 */ 47 static void write_pen_release(int val) 48 { 49 pen_release = val; 50 smp_wmb(); 51 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 52 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); 53 } 54 55 static void __iomem *scu_base_addr(void) 56 { 57 return (void __iomem *)(S5P_VA_SCU); 58 } 59 60 static DEFINE_SPINLOCK(boot_lock); 61 62 static void __cpuinit exynos_secondary_init(unsigned int cpu) 63 { 64 /* 65 * if any interrupts are already enabled for the primary 66 * core (e.g. timer irq), then they will not have been enabled 67 * for us: do so 68 */ 69 gic_secondary_init(0); 70 71 /* 72 * let the primary processor know we're out of the 73 * pen, then head off into the C entry point 74 */ 75 write_pen_release(-1); 76 77 /* 78 * Synchronise with the boot thread. 79 */ 80 spin_lock(&boot_lock); 81 spin_unlock(&boot_lock); 82 } 83 84 static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 85 { 86 unsigned long timeout; 87 88 /* 89 * Set synchronisation state between this boot processor 90 * and the secondary one 91 */ 92 spin_lock(&boot_lock); 93 94 /* 95 * The secondary processor is waiting to be released from 96 * the holding pen - release it, then wait for it to flag 97 * that it has been released by resetting pen_release. 98 * 99 * Note that "pen_release" is the hardware CPU ID, whereas 100 * "cpu" is Linux's internal ID. 101 */ 102 write_pen_release(cpu_logical_map(cpu)); 103 104 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { 105 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 106 S5P_ARM_CORE1_CONFIGURATION); 107 108 timeout = 10; 109 110 /* wait max 10 ms until cpu1 is on */ 111 while ((__raw_readl(S5P_ARM_CORE1_STATUS) 112 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { 113 if (timeout-- == 0) 114 break; 115 116 mdelay(1); 117 } 118 119 if (timeout == 0) { 120 printk(KERN_ERR "cpu1 power enable failed"); 121 spin_unlock(&boot_lock); 122 return -ETIMEDOUT; 123 } 124 } 125 /* 126 * Send the secondary CPU a soft interrupt, thereby causing 127 * the boot monitor to read the system wide flags register, 128 * and branch to the address found there. 129 */ 130 131 timeout = jiffies + (1 * HZ); 132 while (time_before(jiffies, timeout)) { 133 smp_rmb(); 134 135 __raw_writel(virt_to_phys(exynos4_secondary_startup), 136 CPU1_BOOT_REG); 137 gic_raise_softirq(cpumask_of(cpu), 0); 138 139 if (pen_release == -1) 140 break; 141 142 udelay(10); 143 } 144 145 /* 146 * now the secondary core is starting up let it run its 147 * calibrations, then wait for it to finish 148 */ 149 spin_unlock(&boot_lock); 150 151 return pen_release != -1 ? -ENOSYS : 0; 152 } 153 154 /* 155 * Initialise the CPU possible map early - this describes the CPUs 156 * which may be present or become present in the system. 157 */ 158 159 static void __init exynos_smp_init_cpus(void) 160 { 161 void __iomem *scu_base = scu_base_addr(); 162 unsigned int i, ncores; 163 164 if (soc_is_exynos5250()) 165 ncores = 2; 166 else 167 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 168 169 /* sanity check */ 170 if (ncores > nr_cpu_ids) { 171 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 172 ncores, nr_cpu_ids); 173 ncores = nr_cpu_ids; 174 } 175 176 for (i = 0; i < ncores; i++) 177 set_cpu_possible(i, true); 178 179 set_smp_cross_call(gic_raise_softirq); 180 } 181 182 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 183 { 184 if (!soc_is_exynos5250()) 185 scu_enable(scu_base_addr()); 186 187 /* 188 * Write the address of secondary startup into the 189 * system-wide flags register. The boot monitor waits 190 * until it receives a soft interrupt, and then the 191 * secondary CPU branches to this address. 192 */ 193 __raw_writel(virt_to_phys(exynos4_secondary_startup), 194 CPU1_BOOT_REG); 195 } 196 197 struct smp_operations exynos_smp_ops __initdata = { 198 .smp_init_cpus = exynos_smp_init_cpus, 199 .smp_prepare_cpus = exynos_smp_prepare_cpus, 200 .smp_secondary_init = exynos_secondary_init, 201 .smp_boot_secondary = exynos_boot_secondary, 202 #ifdef CONFIG_HOTPLUG_CPU 203 .cpu_die = exynos_cpu_die, 204 #endif 205 }; 206