1347863d4SKrzysztof Kozlowski // SPDX-License-Identifier: GPL-2.0 2347863d4SKrzysztof Kozlowski // 3347863d4SKrzysztof Kozlowski // Copyright (C) 2012 Samsung Electronics. 4347863d4SKrzysztof Kozlowski // Kyungmin Park <kyungmin.park@samsung.com> 5347863d4SKrzysztof Kozlowski // Tomasz Figa <t.figa@samsung.com> 6bca28f8fSTomasz Figa 7bca28f8fSTomasz Figa #include <linux/kernel.h> 8bca28f8fSTomasz Figa #include <linux/io.h> 9bca28f8fSTomasz Figa #include <linux/init.h> 10bca28f8fSTomasz Figa #include <linux/of.h> 11bca28f8fSTomasz Figa #include <linux/of_address.h> 12bca28f8fSTomasz Figa 132b9d9c32STomasz Figa #include <asm/cacheflush.h> 142b9d9c32STomasz Figa #include <asm/cputype.h> 15bca28f8fSTomasz Figa #include <asm/firmware.h> 165445b640STomasz Figa #include <asm/hardware/cache-l2x0.h> 172b9d9c32STomasz Figa #include <asm/suspend.h> 18bca28f8fSTomasz Figa 19b3205deaSSachin Kamat #include "common.h" 20bca28f8fSTomasz Figa #include "smc.h" 21bca28f8fSTomasz Figa 222b9d9c32STomasz Figa #define EXYNOS_BOOT_ADDR 0x8 232b9d9c32STomasz Figa #define EXYNOS_BOOT_FLAG 0xc 242b9d9c32STomasz Figa 25a135e201SBartlomiej Zolnierkiewicz static void exynos_save_cp15(void) 26a135e201SBartlomiej Zolnierkiewicz { 27a135e201SBartlomiej Zolnierkiewicz /* Save Power control and Diagnostic registers */ 28a135e201SBartlomiej Zolnierkiewicz asm ("mrc p15, 0, %0, c15, c0, 0\n" 29a135e201SBartlomiej Zolnierkiewicz "mrc p15, 0, %1, c15, c0, 1\n" 30a135e201SBartlomiej Zolnierkiewicz : "=r" (cp15_save_power), "=r" (cp15_save_diag) 31a135e201SBartlomiej Zolnierkiewicz : : "cc"); 32a135e201SBartlomiej Zolnierkiewicz } 33a135e201SBartlomiej Zolnierkiewicz 340b7778a8SBartlomiej Zolnierkiewicz static int exynos_do_idle(unsigned long mode) 35bca28f8fSTomasz Figa { 360b7778a8SBartlomiej Zolnierkiewicz switch (mode) { 370b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_AFTR: 38a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 39a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 4064fc2a94SFlorian Fainelli writel_relaxed(__pa_symbol(exynos_cpu_resume_ns), 41a135e201SBartlomiej Zolnierkiewicz sysram_ns_base_addr + 0x24); 42458ad21dSBen Dooks writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); 4389366409SBartlomiej Zolnierkiewicz if (soc_is_exynos3250()) { 44af997114SBartlomiej Zolnierkiewicz flush_cache_all(); 4589366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE, 4689366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0); 4789366409SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER, 4889366409SBartlomiej Zolnierkiewicz SMC_POWERSTATE_IDLE, 0); 4989366409SBartlomiej Zolnierkiewicz } else 500b7778a8SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); 510b7778a8SBartlomiej Zolnierkiewicz break; 520b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_SLEEP: 53bca28f8fSTomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 540b7778a8SBartlomiej Zolnierkiewicz } 55bca28f8fSTomasz Figa return 0; 56bca28f8fSTomasz Figa } 57bca28f8fSTomasz Figa 58bca28f8fSTomasz Figa static int exynos_cpu_boot(int cpu) 59bca28f8fSTomasz Figa { 60989ff3fdSKyungmin Park /* 616457158aSChanwoo Choi * Exynos3250 doesn't need to send smc command for secondary CPU boot 626457158aSChanwoo Choi * because Exynos3250 removes WFE in secure mode. 636457158aSChanwoo Choi */ 646457158aSChanwoo Choi if (soc_is_exynos3250()) 656457158aSChanwoo Choi return 0; 666457158aSChanwoo Choi 676457158aSChanwoo Choi /* 68989ff3fdSKyungmin Park * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. 69989ff3fdSKyungmin Park */ 70bca28f8fSTomasz Figa exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 71bca28f8fSTomasz Figa return 0; 72bca28f8fSTomasz Figa } 73bca28f8fSTomasz Figa 74bca28f8fSTomasz Figa static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 75bca28f8fSTomasz Figa { 76b3205deaSSachin Kamat void __iomem *boot_reg; 77b3205deaSSachin Kamat 78b3205deaSSachin Kamat if (!sysram_ns_base_addr) 79b3205deaSSachin Kamat return -ENODEV; 80b3205deaSSachin Kamat 81fe388facSOlof Johansson boot_reg = sysram_ns_base_addr + 0x1c; 82989ff3fdSKyungmin Park 8335e75645SSachin Kamat /* 8435e75645SSachin Kamat * Almost all Exynos-series of SoCs that run in secure mode don't need 8535e75645SSachin Kamat * additional offset for every CPU, with Exynos4412 being the only 8635e75645SSachin Kamat * exception. 8735e75645SSachin Kamat */ 8835e75645SSachin Kamat if (soc_is_exynos4412()) 89989ff3fdSKyungmin Park boot_reg += 4 * cpu; 90bca28f8fSTomasz Figa 91458ad21dSBen Dooks writel_relaxed(boot_addr, boot_reg); 92bca28f8fSTomasz Figa return 0; 93bca28f8fSTomasz Figa } 94bca28f8fSTomasz Figa 951225ad72SBartlomiej Zolnierkiewicz static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr) 961225ad72SBartlomiej Zolnierkiewicz { 971225ad72SBartlomiej Zolnierkiewicz void __iomem *boot_reg; 981225ad72SBartlomiej Zolnierkiewicz 991225ad72SBartlomiej Zolnierkiewicz if (!sysram_ns_base_addr) 1001225ad72SBartlomiej Zolnierkiewicz return -ENODEV; 1011225ad72SBartlomiej Zolnierkiewicz 1021225ad72SBartlomiej Zolnierkiewicz boot_reg = sysram_ns_base_addr + 0x1c; 1031225ad72SBartlomiej Zolnierkiewicz 1041225ad72SBartlomiej Zolnierkiewicz if (soc_is_exynos4412()) 1051225ad72SBartlomiej Zolnierkiewicz boot_reg += 4 * cpu; 1061225ad72SBartlomiej Zolnierkiewicz 107458ad21dSBen Dooks *boot_addr = readl_relaxed(boot_reg); 1081225ad72SBartlomiej Zolnierkiewicz return 0; 1091225ad72SBartlomiej Zolnierkiewicz } 1101225ad72SBartlomiej Zolnierkiewicz 1112b9d9c32STomasz Figa static int exynos_cpu_suspend(unsigned long arg) 1122b9d9c32STomasz Figa { 1132b9d9c32STomasz Figa flush_cache_all(); 1142b9d9c32STomasz Figa outer_flush_all(); 1152b9d9c32STomasz Figa 1162b9d9c32STomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 1172b9d9c32STomasz Figa 1182b9d9c32STomasz Figa pr_info("Failed to suspend the system\n"); 1192b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1202b9d9c32STomasz Figa return 1; 1212b9d9c32STomasz Figa } 1222b9d9c32STomasz Figa 1232b9d9c32STomasz Figa static int exynos_suspend(void) 1242b9d9c32STomasz Figa { 125a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 126a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 1272b9d9c32STomasz Figa 1282b9d9c32STomasz Figa writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 12964fc2a94SFlorian Fainelli writel(__pa_symbol(exynos_cpu_resume_ns), 1302b9d9c32STomasz Figa sysram_ns_base_addr + EXYNOS_BOOT_ADDR); 1312b9d9c32STomasz Figa 1322b9d9c32STomasz Figa return cpu_suspend(0, exynos_cpu_suspend); 1332b9d9c32STomasz Figa } 1342b9d9c32STomasz Figa 1352b9d9c32STomasz Figa static int exynos_resume(void) 1362b9d9c32STomasz Figa { 1372b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1382b9d9c32STomasz Figa 1392b9d9c32STomasz Figa return 0; 1402b9d9c32STomasz Figa } 1412b9d9c32STomasz Figa 142bca28f8fSTomasz Figa static const struct firmware_ops exynos_firmware_ops = { 14303c1b760SArnd Bergmann .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL, 144bca28f8fSTomasz Figa .set_cpu_boot_addr = exynos_set_cpu_boot_addr, 1451225ad72SBartlomiej Zolnierkiewicz .get_cpu_boot_addr = exynos_get_cpu_boot_addr, 146bca28f8fSTomasz Figa .cpu_boot = exynos_cpu_boot, 14703c1b760SArnd Bergmann .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL, 14803c1b760SArnd Bergmann .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, 149bca28f8fSTomasz Figa }; 150bca28f8fSTomasz Figa 1515445b640STomasz Figa static void exynos_l2_write_sec(unsigned long val, unsigned reg) 1525445b640STomasz Figa { 1535445b640STomasz Figa static int l2cache_enabled; 1545445b640STomasz Figa 1555445b640STomasz Figa switch (reg) { 1565445b640STomasz Figa case L2X0_CTRL: 1575445b640STomasz Figa if (val & L2X0_CTRL_EN) { 1585445b640STomasz Figa /* 1595445b640STomasz Figa * Before the cache can be enabled, due to firmware 1605445b640STomasz Figa * design, SMC_CMD_L2X0INVALL must be called. 1615445b640STomasz Figa */ 1625445b640STomasz Figa if (!l2cache_enabled) { 1635445b640STomasz Figa exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 1645445b640STomasz Figa l2cache_enabled = 1; 1655445b640STomasz Figa } 1665445b640STomasz Figa } else { 1675445b640STomasz Figa l2cache_enabled = 0; 1685445b640STomasz Figa } 1695445b640STomasz Figa exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); 1705445b640STomasz Figa break; 1715445b640STomasz Figa 1725445b640STomasz Figa case L2X0_DEBUG_CTRL: 1735445b640STomasz Figa exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); 1745445b640STomasz Figa break; 1755445b640STomasz Figa 1765445b640STomasz Figa default: 1775445b640STomasz Figa WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); 1785445b640STomasz Figa } 1795445b640STomasz Figa } 1805445b640STomasz Figa 1815445b640STomasz Figa static void exynos_l2_configure(const struct l2x0_regs *regs) 1825445b640STomasz Figa { 1835445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, 1845445b640STomasz Figa regs->prefetch_ctrl); 1855445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); 1865445b640STomasz Figa } 1875445b640STomasz Figa 188e0b35c1aSKrzysztof Kozlowski bool __init exynos_secure_firmware_available(void) 189bca28f8fSTomasz Figa { 190bca28f8fSTomasz Figa struct device_node *nd; 191bca28f8fSTomasz Figa const __be32 *addr; 192bca28f8fSTomasz Figa 193bca28f8fSTomasz Figa nd = of_find_compatible_node(NULL, NULL, 194bca28f8fSTomasz Figa "samsung,secure-firmware"); 195bca28f8fSTomasz Figa if (!nd) 196e0b35c1aSKrzysztof Kozlowski return false; 197bca28f8fSTomasz Figa 198bca28f8fSTomasz Figa addr = of_get_address(nd, 0, NULL, NULL); 199bca28f8fSTomasz Figa if (!addr) { 200bca28f8fSTomasz Figa pr_err("%s: No address specified.\n", __func__); 201e0b35c1aSKrzysztof Kozlowski return false; 202bca28f8fSTomasz Figa } 203bca28f8fSTomasz Figa 204e0b35c1aSKrzysztof Kozlowski return true; 205e0b35c1aSKrzysztof Kozlowski } 206e0b35c1aSKrzysztof Kozlowski 207e0b35c1aSKrzysztof Kozlowski void __init exynos_firmware_init(void) 208e0b35c1aSKrzysztof Kozlowski { 209e0b35c1aSKrzysztof Kozlowski if (!exynos_secure_firmware_available()) 210e0b35c1aSKrzysztof Kozlowski return; 211e0b35c1aSKrzysztof Kozlowski 212bca28f8fSTomasz Figa pr_info("Running under secure firmware.\n"); 213bca28f8fSTomasz Figa 214bca28f8fSTomasz Figa register_firmware_ops(&exynos_firmware_ops); 2155445b640STomasz Figa 2165445b640STomasz Figa /* 2175445b640STomasz Figa * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), 2185445b640STomasz Figa * running under secure firmware, require certain registers of L2 2195445b640STomasz Figa * cache controller to be written in secure mode. Here .write_sec 2205445b640STomasz Figa * callback is provided to perform necessary SMC calls. 2215445b640STomasz Figa */ 2225445b640STomasz Figa if (IS_ENABLED(CONFIG_CACHE_L2X0) && 2235445b640STomasz Figa read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 2245445b640STomasz Figa outer_cache.write_sec = exynos_l2_write_sec; 2255445b640STomasz Figa outer_cache.configure = exynos_l2_configure; 2265445b640STomasz Figa } 227bca28f8fSTomasz Figa } 228dc1b9448SBartlomiej Zolnierkiewicz 229dc1b9448SBartlomiej Zolnierkiewicz #define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28) 230dc1b9448SBartlomiej Zolnierkiewicz #define BOOT_MODE_MASK 0x1f 231dc1b9448SBartlomiej Zolnierkiewicz 232dc1b9448SBartlomiej Zolnierkiewicz void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) 233dc1b9448SBartlomiej Zolnierkiewicz { 234dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 235dc1b9448SBartlomiej Zolnierkiewicz 236458ad21dSBen Dooks tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4); 237dc1b9448SBartlomiej Zolnierkiewicz 238dc1b9448SBartlomiej Zolnierkiewicz if (mode & BOOT_MODE_MASK) 239dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~BOOT_MODE_MASK; 240dc1b9448SBartlomiej Zolnierkiewicz 241dc1b9448SBartlomiej Zolnierkiewicz tmp |= mode; 242458ad21dSBen Dooks writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); 243dc1b9448SBartlomiej Zolnierkiewicz } 244dc1b9448SBartlomiej Zolnierkiewicz 245dc1b9448SBartlomiej Zolnierkiewicz void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) 246dc1b9448SBartlomiej Zolnierkiewicz { 247dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 248dc1b9448SBartlomiej Zolnierkiewicz 249458ad21dSBen Dooks tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4); 250dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~mode; 251458ad21dSBen Dooks writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); 252dc1b9448SBartlomiej Zolnierkiewicz } 253