1bca28f8fSTomasz Figa /* 2bca28f8fSTomasz Figa * Copyright (C) 2012 Samsung Electronics. 3bca28f8fSTomasz Figa * Kyungmin Park <kyungmin.park@samsung.com> 4bca28f8fSTomasz Figa * Tomasz Figa <t.figa@samsung.com> 5bca28f8fSTomasz Figa * 6bca28f8fSTomasz Figa * This program is free software,you can redistribute it and/or modify 7bca28f8fSTomasz Figa * it under the terms of the GNU General Public License version 2 as 8bca28f8fSTomasz Figa * published by the Free Software Foundation. 9bca28f8fSTomasz Figa */ 10bca28f8fSTomasz Figa 11bca28f8fSTomasz Figa #include <linux/kernel.h> 12bca28f8fSTomasz Figa #include <linux/io.h> 13bca28f8fSTomasz Figa #include <linux/init.h> 14bca28f8fSTomasz Figa #include <linux/of.h> 15bca28f8fSTomasz Figa #include <linux/of_address.h> 16bca28f8fSTomasz Figa 172b9d9c32STomasz Figa #include <asm/cacheflush.h> 182b9d9c32STomasz Figa #include <asm/cputype.h> 19bca28f8fSTomasz Figa #include <asm/firmware.h> 205445b640STomasz Figa #include <asm/hardware/cache-l2x0.h> 212b9d9c32STomasz Figa #include <asm/suspend.h> 22bca28f8fSTomasz Figa 23bca28f8fSTomasz Figa #include <mach/map.h> 24bca28f8fSTomasz Figa 25b3205deaSSachin Kamat #include "common.h" 26bca28f8fSTomasz Figa #include "smc.h" 27bca28f8fSTomasz Figa 282b9d9c32STomasz Figa #define EXYNOS_SLEEP_MAGIC 0x00000bad 29a135e201SBartlomiej Zolnierkiewicz #define EXYNOS_AFTR_MAGIC 0xfcba0d10 302b9d9c32STomasz Figa #define EXYNOS_BOOT_ADDR 0x8 312b9d9c32STomasz Figa #define EXYNOS_BOOT_FLAG 0xc 322b9d9c32STomasz Figa 33a135e201SBartlomiej Zolnierkiewicz static void exynos_save_cp15(void) 34a135e201SBartlomiej Zolnierkiewicz { 35a135e201SBartlomiej Zolnierkiewicz /* Save Power control and Diagnostic registers */ 36a135e201SBartlomiej Zolnierkiewicz asm ("mrc p15, 0, %0, c15, c0, 0\n" 37a135e201SBartlomiej Zolnierkiewicz "mrc p15, 0, %1, c15, c0, 1\n" 38a135e201SBartlomiej Zolnierkiewicz : "=r" (cp15_save_power), "=r" (cp15_save_diag) 39a135e201SBartlomiej Zolnierkiewicz : : "cc"); 40a135e201SBartlomiej Zolnierkiewicz } 41a135e201SBartlomiej Zolnierkiewicz 420b7778a8SBartlomiej Zolnierkiewicz static int exynos_do_idle(unsigned long mode) 43bca28f8fSTomasz Figa { 440b7778a8SBartlomiej Zolnierkiewicz switch (mode) { 450b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_AFTR: 46a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 47a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 48a135e201SBartlomiej Zolnierkiewicz __raw_writel(virt_to_phys(exynos_cpu_resume_ns), 49a135e201SBartlomiej Zolnierkiewicz sysram_ns_base_addr + 0x24); 50a135e201SBartlomiej Zolnierkiewicz __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); 510b7778a8SBartlomiej Zolnierkiewicz exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); 520b7778a8SBartlomiej Zolnierkiewicz break; 530b7778a8SBartlomiej Zolnierkiewicz case FW_DO_IDLE_SLEEP: 54bca28f8fSTomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 550b7778a8SBartlomiej Zolnierkiewicz } 56bca28f8fSTomasz Figa return 0; 57bca28f8fSTomasz Figa } 58bca28f8fSTomasz Figa 59bca28f8fSTomasz Figa static int exynos_cpu_boot(int cpu) 60bca28f8fSTomasz Figa { 61989ff3fdSKyungmin Park /* 626457158aSChanwoo Choi * Exynos3250 doesn't need to send smc command for secondary CPU boot 636457158aSChanwoo Choi * because Exynos3250 removes WFE in secure mode. 646457158aSChanwoo Choi */ 656457158aSChanwoo Choi if (soc_is_exynos3250()) 666457158aSChanwoo Choi return 0; 676457158aSChanwoo Choi 686457158aSChanwoo Choi /* 69989ff3fdSKyungmin Park * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. 70989ff3fdSKyungmin Park * But, Exynos4212 has only one secondary CPU so second parameter 71989ff3fdSKyungmin Park * isn't used for informing secure firmware about CPU id. 72989ff3fdSKyungmin Park */ 73989ff3fdSKyungmin Park if (soc_is_exynos4212()) 74989ff3fdSKyungmin Park cpu = 0; 75989ff3fdSKyungmin Park 76bca28f8fSTomasz Figa exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 77bca28f8fSTomasz Figa return 0; 78bca28f8fSTomasz Figa } 79bca28f8fSTomasz Figa 80bca28f8fSTomasz Figa static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 81bca28f8fSTomasz Figa { 82b3205deaSSachin Kamat void __iomem *boot_reg; 83b3205deaSSachin Kamat 84b3205deaSSachin Kamat if (!sysram_ns_base_addr) 85b3205deaSSachin Kamat return -ENODEV; 86b3205deaSSachin Kamat 87fe388facSOlof Johansson boot_reg = sysram_ns_base_addr + 0x1c; 88989ff3fdSKyungmin Park 8935e75645SSachin Kamat /* 9035e75645SSachin Kamat * Almost all Exynos-series of SoCs that run in secure mode don't need 9135e75645SSachin Kamat * additional offset for every CPU, with Exynos4412 being the only 9235e75645SSachin Kamat * exception. 9335e75645SSachin Kamat */ 9435e75645SSachin Kamat if (soc_is_exynos4412()) 95989ff3fdSKyungmin Park boot_reg += 4 * cpu; 96bca28f8fSTomasz Figa 97bca28f8fSTomasz Figa __raw_writel(boot_addr, boot_reg); 98bca28f8fSTomasz Figa return 0; 99bca28f8fSTomasz Figa } 100bca28f8fSTomasz Figa 1012b9d9c32STomasz Figa static int exynos_cpu_suspend(unsigned long arg) 1022b9d9c32STomasz Figa { 1032b9d9c32STomasz Figa flush_cache_all(); 1042b9d9c32STomasz Figa outer_flush_all(); 1052b9d9c32STomasz Figa 1062b9d9c32STomasz Figa exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 1072b9d9c32STomasz Figa 1082b9d9c32STomasz Figa pr_info("Failed to suspend the system\n"); 1092b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1102b9d9c32STomasz Figa return 1; 1112b9d9c32STomasz Figa } 1122b9d9c32STomasz Figa 1132b9d9c32STomasz Figa static int exynos_suspend(void) 1142b9d9c32STomasz Figa { 115a135e201SBartlomiej Zolnierkiewicz if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 116a135e201SBartlomiej Zolnierkiewicz exynos_save_cp15(); 1172b9d9c32STomasz Figa 1182b9d9c32STomasz Figa writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1192b9d9c32STomasz Figa writel(virt_to_phys(exynos_cpu_resume_ns), 1202b9d9c32STomasz Figa sysram_ns_base_addr + EXYNOS_BOOT_ADDR); 1212b9d9c32STomasz Figa 1222b9d9c32STomasz Figa return cpu_suspend(0, exynos_cpu_suspend); 1232b9d9c32STomasz Figa } 1242b9d9c32STomasz Figa 1252b9d9c32STomasz Figa static int exynos_resume(void) 1262b9d9c32STomasz Figa { 1272b9d9c32STomasz Figa writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 1282b9d9c32STomasz Figa 1292b9d9c32STomasz Figa return 0; 1302b9d9c32STomasz Figa } 1312b9d9c32STomasz Figa 132bca28f8fSTomasz Figa static const struct firmware_ops exynos_firmware_ops = { 13303c1b760SArnd Bergmann .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL, 134bca28f8fSTomasz Figa .set_cpu_boot_addr = exynos_set_cpu_boot_addr, 135bca28f8fSTomasz Figa .cpu_boot = exynos_cpu_boot, 13603c1b760SArnd Bergmann .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL, 13703c1b760SArnd Bergmann .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, 138bca28f8fSTomasz Figa }; 139bca28f8fSTomasz Figa 1405445b640STomasz Figa static void exynos_l2_write_sec(unsigned long val, unsigned reg) 1415445b640STomasz Figa { 1425445b640STomasz Figa static int l2cache_enabled; 1435445b640STomasz Figa 1445445b640STomasz Figa switch (reg) { 1455445b640STomasz Figa case L2X0_CTRL: 1465445b640STomasz Figa if (val & L2X0_CTRL_EN) { 1475445b640STomasz Figa /* 1485445b640STomasz Figa * Before the cache can be enabled, due to firmware 1495445b640STomasz Figa * design, SMC_CMD_L2X0INVALL must be called. 1505445b640STomasz Figa */ 1515445b640STomasz Figa if (!l2cache_enabled) { 1525445b640STomasz Figa exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 1535445b640STomasz Figa l2cache_enabled = 1; 1545445b640STomasz Figa } 1555445b640STomasz Figa } else { 1565445b640STomasz Figa l2cache_enabled = 0; 1575445b640STomasz Figa } 1585445b640STomasz Figa exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); 1595445b640STomasz Figa break; 1605445b640STomasz Figa 1615445b640STomasz Figa case L2X0_DEBUG_CTRL: 1625445b640STomasz Figa exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); 1635445b640STomasz Figa break; 1645445b640STomasz Figa 1655445b640STomasz Figa default: 1665445b640STomasz Figa WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); 1675445b640STomasz Figa } 1685445b640STomasz Figa } 1695445b640STomasz Figa 1705445b640STomasz Figa static void exynos_l2_configure(const struct l2x0_regs *regs) 1715445b640STomasz Figa { 1725445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, 1735445b640STomasz Figa regs->prefetch_ctrl); 1745445b640STomasz Figa exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); 1755445b640STomasz Figa } 1765445b640STomasz Figa 177bca28f8fSTomasz Figa void __init exynos_firmware_init(void) 178bca28f8fSTomasz Figa { 179bca28f8fSTomasz Figa struct device_node *nd; 180bca28f8fSTomasz Figa const __be32 *addr; 181bca28f8fSTomasz Figa 182bca28f8fSTomasz Figa nd = of_find_compatible_node(NULL, NULL, 183bca28f8fSTomasz Figa "samsung,secure-firmware"); 184bca28f8fSTomasz Figa if (!nd) 185bca28f8fSTomasz Figa return; 186bca28f8fSTomasz Figa 187bca28f8fSTomasz Figa addr = of_get_address(nd, 0, NULL, NULL); 188bca28f8fSTomasz Figa if (!addr) { 189bca28f8fSTomasz Figa pr_err("%s: No address specified.\n", __func__); 190bca28f8fSTomasz Figa return; 191bca28f8fSTomasz Figa } 192bca28f8fSTomasz Figa 193bca28f8fSTomasz Figa pr_info("Running under secure firmware.\n"); 194bca28f8fSTomasz Figa 195bca28f8fSTomasz Figa register_firmware_ops(&exynos_firmware_ops); 1965445b640STomasz Figa 1975445b640STomasz Figa /* 1985445b640STomasz Figa * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), 1995445b640STomasz Figa * running under secure firmware, require certain registers of L2 2005445b640STomasz Figa * cache controller to be written in secure mode. Here .write_sec 2015445b640STomasz Figa * callback is provided to perform necessary SMC calls. 2025445b640STomasz Figa */ 2035445b640STomasz Figa if (IS_ENABLED(CONFIG_CACHE_L2X0) && 2045445b640STomasz Figa read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 2055445b640STomasz Figa outer_cache.write_sec = exynos_l2_write_sec; 2065445b640STomasz Figa outer_cache.configure = exynos_l2_configure; 2075445b640STomasz Figa } 208bca28f8fSTomasz Figa } 209dc1b9448SBartlomiej Zolnierkiewicz 210dc1b9448SBartlomiej Zolnierkiewicz #define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28) 211dc1b9448SBartlomiej Zolnierkiewicz #define BOOT_MODE_MASK 0x1f 212dc1b9448SBartlomiej Zolnierkiewicz 213dc1b9448SBartlomiej Zolnierkiewicz void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) 214dc1b9448SBartlomiej Zolnierkiewicz { 215dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 216dc1b9448SBartlomiej Zolnierkiewicz 217dc1b9448SBartlomiej Zolnierkiewicz tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 218dc1b9448SBartlomiej Zolnierkiewicz 219dc1b9448SBartlomiej Zolnierkiewicz if (mode & BOOT_MODE_MASK) 220dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~BOOT_MODE_MASK; 221dc1b9448SBartlomiej Zolnierkiewicz 222dc1b9448SBartlomiej Zolnierkiewicz tmp |= mode; 223dc1b9448SBartlomiej Zolnierkiewicz __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 224dc1b9448SBartlomiej Zolnierkiewicz } 225dc1b9448SBartlomiej Zolnierkiewicz 226dc1b9448SBartlomiej Zolnierkiewicz void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) 227dc1b9448SBartlomiej Zolnierkiewicz { 228dc1b9448SBartlomiej Zolnierkiewicz unsigned int tmp; 229dc1b9448SBartlomiej Zolnierkiewicz 230dc1b9448SBartlomiej Zolnierkiewicz tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 231dc1b9448SBartlomiej Zolnierkiewicz tmp &= ~mode; 232dc1b9448SBartlomiej Zolnierkiewicz __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 233dc1b9448SBartlomiej Zolnierkiewicz } 234